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From:   Andy Lutomirski <luto@kernel.org>
Date:   Thu, 3 Sep 2020 07:54:05 -0700
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Subject: Re: [PATCH v11 6/9] x86/cet: Add PTRACE interface for CET
To:     Dave Hansen <dave.hansen@intel.com>
Cc:     "Yu, Yu-cheng" <yu-cheng.yu@intel.com>,
        Jann Horn <jannh@google.com>,
        "the arch/x86 maintainers" <x86@kernel.org>,
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On Thu, Sep 3, 2020 at 7:27 AM Dave Hansen <dave.hansen@intel.com> wrote:
>
> On 9/2/20 9:35 PM, Andy Lutomirski wrote:
> >>>>>> +       fpu__prepare_read(fpu);
> >>>>>> +       cetregs =3D get_xsave_addr(&fpu->state.xsave, XFEATURE_CET=
_USER);
> >>>>>> +       if (!cetregs)
> >>>>>> +               return -EFAULT;
> >>>>> Can this branch ever be hit without a kernel bug? If yes, I think
> >>>>> -EFAULT is probably a weird error code to choose here. If no, this
> >>>>> should probably use WARN_ON(). Same thing in cetregs_set().
> >>>> When a thread is not CET-enabled, its CET state does not exist.  I l=
ooked at EFAULT, and it means "Bad address".  Maybe this can be ENODEV, whi=
ch means "No such device"?
> > Having read the code, I=E2=80=99m unconvinced. It looks like a get_xsav=
e_addr() failure means =E2=80=9Cstate not saved; task sees INIT state=E2=80=
=9D.  So *maybe* it=E2=80=99s reasonable -ENODEV this, but I=E2=80=99m not =
really convinced. I tend to think we should return the actual INIT state an=
d that we should permit writes and handle them correctly.
>
> PTRACE is asking for access to the values in the *registers*, not for
> the value in the kernel XSAVE buffer.  We just happen to only have the
> kernel XSAVE buffer around.
>
> If we want to really support PTRACE we have to allow the registers to be
> get/set, regardless of what state they are in, INIT state or not.  So,
> yeah I agree with Andy.

I think the core dump code gets here, too, so the values might be in
registers as well.  I hope that fpu__prepare_read() does the right
thing in this case.

--Andy