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[23.128.96.18]) by mx.google.com with ESMTP id r2si2312324edx.134.2020.09.03.08.39.01; Thu, 03 Sep 2020 08:39:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MNMsCdV5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728508AbgICPiZ (ORCPT + 99 others); Thu, 3 Sep 2020 11:38:25 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:59884 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726368AbgICPiW (ORCPT ); Thu, 3 Sep 2020 11:38:22 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 083DLLZQ050729; Thu, 3 Sep 2020 08:21:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599139281; bh=eaAGcywfA/M9ZZjeUNXOrgGSq2797CckUuCriGH8Uuc=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=MNMsCdV5eFxqTbHQEGUfTnxVk1GKrfbWvYHxcl4zuXlmYQIyijdVthGQvy4xp5x6E iLElFY2zncoMi5c0m0evL/pyrxd1ffhgCYLQkZIdyQF2O4HhMHVT8plbKLZx7ogZ4N eNCFMNl5i43hiAc9DxJqnkf4d+in1dcAHNlkh998= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 083DLL8d064551 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Sep 2020 08:21:21 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 3 Sep 2020 08:21:21 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 3 Sep 2020 08:21:21 -0500 Received: from [10.250.235.166] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 083DLHG1130034; Thu, 3 Sep 2020 08:21:18 -0500 Subject: Re: [PATCH V2 4/8] arm64: dts: ti: k3-am65*: Use generic clock for syscon clock names To: Nishanth Menon , Rob Herring , Tero Kristo CC: , , , Suman Anna , , , References: <20200901223059.14801-1-nm@ti.com> <20200903130015.21361-5-nm@ti.com> From: Vignesh Raghavendra Message-ID: Date: Thu, 3 Sep 2020 18:51:17 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200903130015.21361-5-nm@ti.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/3/20 6:30 PM, Nishanth Menon wrote: > serdes and ehrpwm_tbclk nodes should be using clock@ naming for nodes > following standard conventions of device tree (section 2.2.2 Generic > Names recommendation in [1]). > > [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 > > Suggested-by: Suman Anna > Signed-off-by: Nishanth Menon > Reviewed-by: Lokesh Vutla > Acked-by: Suman Anna > --- > Change: > v2: added ehrpwm_tbclk based on review comments. > v1: https://lore.kernel.org/linux-arm-kernel/20200901223059.14801-3-nm@ti.com/ > > arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > index a2fc508e59a6..63a1299cb0b2 100644 > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > @@ -327,12 +327,12 @@ > reg = <0x00000210 0x4>; > }; > > - serdes0_clk: serdes_clk@4080 { > + serdes0_clk: clock@4080 { > compatible = "syscon"; > reg = <0x00004080 0x4>; > }; > > - serdes1_clk: serdes_clk@4090 { > + serdes1_clk: clock@4090 { > compatible = "syscon"; > reg = <0x00004090 0x4>; > }; > @@ -349,7 +349,7 @@ > reg = <0x0000041e0 0x14>; > }; > > - ehrpwm_tbclk: syscon@4140 { > + ehrpwm_tbclk: clock@4140 { > compatible = "ti,am654-ehrpwm-tbclk", "syscon"; > reg = <0x4140 0x18>; > #clock-cells = <1>; > Acked-by: Vignesh Raghavendra