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[23.128.96.18]) by mx.google.com with ESMTP id z2si4528620eju.389.2020.09.04.05.32.33; Fri, 04 Sep 2020 05:32:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LfGh/u44"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730237AbgIDM3Y (ORCPT + 99 others); Fri, 4 Sep 2020 08:29:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729741AbgIDM3O (ORCPT ); Fri, 4 Sep 2020 08:29:14 -0400 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36623C061244 for ; Fri, 4 Sep 2020 05:29:12 -0700 (PDT) Received: by mail-lf1-x141.google.com with SMTP id b12so3739784lfp.9 for ; Fri, 04 Sep 2020 05:29:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language; bh=PPvJYpMWtxF9P+f2vmUfRAeP5aXxo/Q2XHW7K7bvGS0=; b=LfGh/u44eDSVP09IaHsTKKi/EZwNdmpDmWeI7J7yRLL19J7iK7PjBYg0UvKgcB5/lg 0iYoh+ww3Hd1bohT2l/R2Z/C2i3Ro8RP3TLdXox34a583mFCmhV0601SOjSFgzL/KUKE g6Lyvp8msHfIY4OEfo2zU+acjsmw0JlqBoZSMAIOHinVwVU+vR0yvB3ipnqUU5gHPnUG jS1G3P+h8DWx/QZGL1jr+gOGom3VBxyGbYkSaI6I5vv40QSIpQec8sb3Sc/BoVuO56nc 13GiK80XgbcoA4hRXYuYnxB3p0xOFiQDuiFChLrJ5yQ2SU5YT9HINmUwI0J8/qlBcvyA 1hrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language; bh=PPvJYpMWtxF9P+f2vmUfRAeP5aXxo/Q2XHW7K7bvGS0=; b=UMP//smvsuxqQTM2H2hid1qsjUtiuvng1tR3+V4afR7hSfoXdmoQ4s7Co8l0MyO9+N ZlBfwfLHd1n9yoNQjytUMDEVo8W1L5b9CmL7HN+pXbGHVybBD0zLRXZceVzbMLLsyD2Z q5zDBLMcOnuU9BZ57v44f730ZSy0SVD21ewvKwuGsizL6vxT7mtNoRKzlVdw5Dl3949A Z0ZgWznUngbaGA10tNXgRUQIGaav4tNimVxcJIaTgqnTSdm3+J922SQQiwgMDs1A3O4M vljwfdNWeSBxm7uVKMYr6bLkSz8a32nD360/u4Lres7ELN8A4Hs5eUzAgEzBEg8k1I5b EKaw== X-Gm-Message-State: AOAM533ZWUnlBBf4THSxXp3F4/8uXMJWg/UVUjPQcYy96C+cK8Hn6m5b C712o7JB8/ddYi18EL7hRVolCQ== X-Received: by 2002:a19:f513:: with SMTP id j19mr3761152lfb.174.1599222549949; Fri, 04 Sep 2020 05:29:09 -0700 (PDT) Received: from [192.168.1.211] ([188.162.64.166]) by smtp.gmail.com with ESMTPSA id y17sm338639ljm.55.2020.09.04.05.29.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Sep 2020 05:29:09 -0700 (PDT) Subject: Re: [PATCH v2 07/10] phy: qcom-qmp: Add support for DP in USB3+DP combo phy To: Jonathan Marek , Stephen Boyd , Kishon Vijay Abraham I , Vinod Koul Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jeykumar Sankaran , Chandan Uddaraju , Vara Reddy , Tanmay Shah , Bjorn Andersson , Manu Gautam , Sandeep Maheswaram , Douglas Anderson , Sean Paul , Stephen Boyd , Rob Clark References: <20200902230215.3452712-1-swboyd@chromium.org> <20200902230215.3452712-8-swboyd@chromium.org> From: Dmitry Baryshkov Message-ID: <9f99cc8b-2cfd-280f-e52a-23d098934a11@linaro.org> Date: Fri, 4 Sep 2020 15:29:09 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/mixed; boundary="------------42528826E690EDBD52217A90" Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is a multi-part message in MIME format. --------------42528826E690EDBD52217A90 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit On 03/09/2020 23:43, Jonathan Marek wrote: > On 9/2/20 7:02 PM, Stephen Boyd wrote: >> Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy >> driver. We already have support for the USB3 part of the combo phy, so >> most additions are for the DP phy. >> >> Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, >> power on, power off, and exit functions that the common phy framework >> expects so that the DP phy can add even more phy ops like >> phy_calibrate() and phy_configure(). This allows us to initialize the DP >> PHY and configure the AUX channel before powering on the PHY at the link >> rate that was negotiated during link training. >> >> The general design is as follows: >> >>    1) DP controller calls phy_init() to initialize the PHY and configure >>    the dp_com register region. >> >>    2) DP controller calls phy_configure() to tune the link rate and >>    voltage swing and pre-emphasis settings. >> >>    3) DP controller calls phy_power_on() to enable the PLL and power on >>    the phy. >> >>    4) DP controller calls phy_configure() again to tune the voltage swing >>    and pre-emphasis settings determind during link training. >> >>    5) DP controller calls phy_calibrate() some number of times to change >>    the aux settings if the aux channel times out during link training. >> >>    6) DP controller calls phy_power_off() if the link rate is to be >>    changed and goes back to step 2 to try again at a different link rate. >> >>    5) DP controller calls phy_power_off() and then phy_exit() to power >>    down the PHY when it is done. >> >> The DP PHY contains a PLL that is different from the one used for the >> USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk >> output from the DP PLL after going through various dividers. Introduce >> clk ops for these two clks that just tell the child clks what the >> frequency of the pixel and link are. When the phy link rate is >> configured we call clk_set_rate() to update the child clks in the >> display clk controller on what rate is in use. The clk frequencies >> always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or >> 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or >> HBR3) so we simply store the link rate and use that to calculate the clk >> frequencies. >> >> The PLL enable sequence is a little different from other QMP phy PLLs so >> we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called >> from phy_power_on(). This should probably be split out better so that >> each phy has a way to run the final PLL/PHY enable sequence. >> >> This code is based on a submission of this phy and PLL in the drm >> subsystem. > > I updated my upstream-based sm8150/sm8250 displayport stack [1] to use > these patches. I have tried your branch on my RB5 with two different dongles. Both dongles provide the same behaviour: - on first plug I see VDM Tx errors, - after I unplug and replug the dongle, PD phy seems to be stuck on sending capabilities. See attached logs. Also I had to add typec_unregister_port(port->typec_port); to IS_ERR(alt) in your tcpm.c hack. I'm currently finishing the driver for the mux/redriver, will retry testing afterwards. > This commit [2] might interest you, so that you can consider what needs > to change between v3 and v4 PHYs. Note some of the V4 registers have the > same address as V3, so the diff could be smaller. > > Do you have any plan for dealing with the SS PHY and DP PHY conflicting > with each other? For example, PHY_MODE_CTRL needs to be "DP_MODE" for > 4-lane DP, "DP_MODE | USB3_MODE" for 2-lane DP + USB3, and (AFAIK) > "USB3_MODE" for superspeedplus usb (and it seems this gates some clocks, > so you can't read/write dp tx2 registers in 2-lane DP mode for example). > From your cover letter it sounds like this isn't relevant to your > hardware, but it looks like both PHYs are writing to the dp_com region > which is still problematic. (in the branch I linked, I disabled the SS > PHY to test the DP PHY) > > Also some issues I noticed: > - used QSERDES_COM_RESETSM_CNTRL instead of > QSERDES_V3_COM_RESETSM_CNTRL2, which has different value > - in sc7180_dpphy_cfg, .regs is NULL, which results in NULL references > > [1] https://github.com/flto/linux/commits/sm8x50-hdk-display > [2] > https://github.com/flto/linux/commit/ccf56912bd5e652b4daebec1300961a9d51342b1 > -- With best wishes Dmitry --------------42528826E690EDBD52217A90 Content-Type: text/plain; charset=UTF-8; name="dp-hdmi.txt" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="dp-hdmi.txt" WyAgIDQzLjg0NzI5M10gVFlQRUM6IFZCVVMgb2ZmClsgICA0My44NTAyMTNdIFRZUEVDOiBD QzE6IDAgLT4gMCwgQ0MyOiAwIC0+IDIgW3N0YXRlIFRPR0dMSU5HLCBwb2xhcml0eSAwLCBj b25uZWN0ZWRdClsgICA0My44NTgwNzVdIFRZUEVDOiBzdGF0ZSBjaGFuZ2UgVE9HR0xJTkcg LT4gU1JDX0FUVEFDSF9XQUlUClsgICA0My44NjM4MTddIFRZUEVDOiBWQlVTIG9mZgpbICAg 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