Received: by 2002:a05:6a10:22f:0:0:0:0 with SMTP id 15csp1288175pxk; Fri, 4 Sep 2020 05:59:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/XwJ7p7WSm7V8gD2dmuuN789qaquQPBAj6mkkeeO+Bqd9VyW8C3LEvWUE3qTBaSaYRytY X-Received: by 2002:aa7:db89:: with SMTP id u9mr8044961edt.267.1599224359407; Fri, 04 Sep 2020 05:59:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599224359; cv=none; d=google.com; s=arc-20160816; b=DbJHD1S4D+ygoy5JoCsgwxKkeUjQ4yW2JYb5zsnpgP9vMw9sMADQZTBRrNINAEnJ55 DHyLT71nbOVt8xGyUWbLXbZsq2SRzXmk4oUqV/yeS/hRnqbZPbtetQFoMmPTRahssBGg f/4RPuq8NVrxAO0jF27P4RYJ3tylXSZx46SRajHKSzDuKNV8K49tIcODsH03H8u+qU+R jUs1PRrxPcW4EzXBiMtye5m9Mm99wt2txVLWuwKNTSERXRTcovPS5qi3hRmNIE66O/7d vCbqZviDN1Ixisjf0aLSMLmtqvaQI+OkuMNGOhpCFQ9ZRJJNJnZciTDUsHnsR5/uqLQO xT3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=yv8vkjDQK6hcRmOjhA1B4LKV5dcNKUU+lKopTGFxDEk=; b=qF6pLLLxpPmJyoitOayrufcP8IiztUrzN/0TmoSR7bQE41xugwXgMelmzmoQLLJrdn 44Ch0EuRK7R0nDJ9zG6mgJJ30OE+tgZCGXnzKheKclMbUTStVfHfzNehfuFd6BN1Rkre H7MjuY3rSeDCg8uc+odISx21H69G8a5fJhLJBuICp3bkEzp3qD3xTiu/un/a4TPfYmgn Ia/PYiKApIoZqqtyYJ6sQ6d/l8h2tDJYd7E4NbqHAxGxQzX+d4XDAAlnFXR3uZlyGzjA Zw77ubcBzXtFsgbVqIeiYdPEH+EZiNsP3na4QjKchY9hxdGIt0woaC7WY7XLCnnkTpj1 ZJnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=d0c4e8pn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l14si4197960edv.603.2020.09.04.05.58.56; Fri, 04 Sep 2020 05:59:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=d0c4e8pn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730301AbgIDMzj (ORCPT + 99 others); Fri, 4 Sep 2020 08:55:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730010AbgIDMzh (ORCPT ); Fri, 4 Sep 2020 08:55:37 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1E98C061244 for ; Fri, 4 Sep 2020 05:55:36 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id k15so6622211wrn.10 for ; Fri, 04 Sep 2020 05:55:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=yv8vkjDQK6hcRmOjhA1B4LKV5dcNKUU+lKopTGFxDEk=; b=d0c4e8pnx/zw8L1LUX1IDKWgDaOOcFOwkGN7pDeTnRSV3HcfbvwR2pF65F33Qq2OrP x0L8nWU/KikfnXLm0ad7qfVo32XRlkxz7Z0eDlEsVHr+cfAv784G2m9LTVfLv+L0f7y/ /N0KuRUbHfIOdbBvB07yBYVOSJDW1Zi5LWqy6KbFBa/6nwLkxkd9MKkd95bfh20BkAeN RRubpy7nee7IrN1eT3+dighUN7LxYPJNkUVJ30yLVmCThHcyJhG2YMk/uW+8O+9hXuxX T76cIDTMe6zOR1Ub9D9DCmA+3lE1EuogygFRlm3pCq0Ql2rw04CMAx81n9gC7E/XmE6j jONQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=yv8vkjDQK6hcRmOjhA1B4LKV5dcNKUU+lKopTGFxDEk=; b=WmWwXNX16edlcxNOZ+uaUJTdcbeDqnK6CJ9nCUeWAhLv9IJ5Ae5Flo6Yc8HExnDk1l S2PbrBvQWkNIVUKM5WPGHbnl/N7QnfzQ1Po/w0aUiVkrdnr76MOHHbucQvapyuaUApYv HtLQtwI9AqsTL3pQmf8nycIxhvpTBRgvSSTR9rgFwCqtMi1kve71e8Uu3BNgZaPGemDC KAzJZlMVp1+nrT0fKMv+fMxaYLxEtH9pX6s4L5kCJ81KGuHA30FMmR2pH742ViDzkH2m x2+wDV7NbGbKILDcQbd0KZQxrJi1X2SU6f9WRT7P2+42Bj0RGVwdqLcpf0Z+RxtQMYKm AZEA== X-Gm-Message-State: AOAM533ijAYa5XycBgswM11RtFLMeCn4OgJip3XleUbVVMjACO8TGmWV 4KSXOsiRW+F4BJ2J+J2xUE/DZA== X-Received: by 2002:a5d:5486:: with SMTP id h6mr7572543wrv.415.1599224134577; Fri, 04 Sep 2020 05:55:34 -0700 (PDT) Received: from bender.baylibre.local ([2a01:e35:2ec0:82b0:5405:9623:e2f1:b2ac]) by smtp.gmail.com with ESMTPSA id z15sm11026236wrv.94.2020.09.04.05.55.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2020 05:55:33 -0700 (PDT) From: Neil Armstrong To: a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@siol.net Cc: yannick.fertre@st.com, heiko.stuebner@theobroma-systems.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, Neil Armstrong Subject: [PATCH] drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate Date: Fri, 4 Sep 2020 14:55:31 +0200 Message-Id: <20200904125531.15248-1-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 25 +++++++++++++++---- include/drm/bridge/dw_mipi_dsi.h | 1 + 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index d580b2aa4ce9..31fc965c66fd 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -562,15 +562,30 @@ static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) { + const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; + unsigned int esc_rate; /* in MHz */ + u32 esc_clk_division; + int ret; + /* * The maximum permitted escape clock is 20MHz and it is derived from - * lanebyteclk, which is running at "lane_mbps / 8". Thus we want: - * - * (lane_mbps >> 3) / esc_clk_division < 20 + * lanebyteclk, which is running at "lane_mbps / 8". + */ + if (phy_ops->get_esc_clk_rate) { + ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data, + &esc_rate); + if (ret) + DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n"); + } else + esc_rate = 20; /* Default to 20MHz */ + + /* + * We want : + * (lane_mbps >> 3) / esc_clk_division < X * which is: - * (lane_mbps >> 3) / 20 > esc_clk_division + * (lane_mbps >> 3) / X > esc_clk_division */ - u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; + esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1; dsi_write(dsi, DSI_PWR_UP, RESET); diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h index b0e390b3288e..bda8aa7c2280 100644 --- a/include/drm/bridge/dw_mipi_dsi.h +++ b/include/drm/bridge/dw_mipi_dsi.h @@ -36,6 +36,7 @@ struct dw_mipi_dsi_phy_ops { unsigned int *lane_mbps); int (*get_timing)(void *priv_data, unsigned int lane_mbps, struct dw_mipi_dsi_dphy_timing *timing); + int (*get_esc_clk_rate)(void *priv_data, unsigned int *esc_clk_rate); }; struct dw_mipi_dsi_host_ops { -- 2.22.0