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[23.128.96.18]) by mx.google.com with ESMTP id q5si1413687eji.118.2020.09.04.07.01.34; Fri, 04 Sep 2020 07:01:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=cB+oUopl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730694AbgIDN5h (ORCPT + 99 others); Fri, 4 Sep 2020 09:57:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730686AbgIDN50 (ORCPT ); Fri, 4 Sep 2020 09:57:26 -0400 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80368C061244; Fri, 4 Sep 2020 06:57:26 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id c2so8023548ljj.12; Fri, 04 Sep 2020 06:57:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hoXXqd8o1tMS9WjpaTwn6JIuueqXzxlr8fJ8ASQWetI=; b=cB+oUoplgC6GyIFVtcLejHJV/VcvpasFda3aA7jC4OvseF5QmxCPplLaZ/3CmGESHG I/lemT2CDw1SJ22GzYzixEWVeN+w+9XBLwPsmUCFB49z93hHInL+8ABC4pbL3ulr07NU zeQYE3deleybCtihNK3FHdJ+iJ4/pHB9jWuxoQrQO+ghVZgxcGeLBfSjSjBxZjb3nPL6 d+2As+CqoO0AIHUB0vCch7UcVZHjSJ1KLDeiqPU/xq5uJ/8eNuW1aGch4TT4n8wRfAtl 2LjxqwFcjdB0sVFUbjxnBP39gVu270eetm1ZB1ZgsFOCIMUNSSSoqHXCLqfZfRnoJRlD 6fNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hoXXqd8o1tMS9WjpaTwn6JIuueqXzxlr8fJ8ASQWetI=; b=E5q60vQDu1T3IbgY6LXBcpItHoNzruU5jhVgbJeS3nLBieC7GJfXu3dHX0skQiQWCu sulOHWSX67DWgTxCFl9Cbc9LJdvOVtGe4xr0Tovoe7D9bS3f5NRrUlQIBc9MHwwNiPqc eoQiNwxFIXKct9dkbKkJ9GmL+IgkZjMtJzZb/fXlf0sn2rhiXMr7foL7dqwrF2LjIC3p IWZc2PBUuJ6uY/RPjoQUqAKVwxZGyLIQRwoevF5Are8rxVkTd47wAfKjugGFeTzTUXnb 9HptX3ecjaTLkGa/CM6NdT2YdvO4jGDQg5+0bEWDDWjyxnTghmmYevJE1jWG5yoVg5oS jfQA== X-Gm-Message-State: AOAM533OfZg0gft6/k/P1wuMX8GKIcWiVhlrp2c55rx4y5ms5qTRDGrx lcbE1nttlUXSyywR8SOSqHMhJphUuxD/jJCRZfmDAc1I X-Received: by 2002:a2e:390a:: with SMTP id g10mr3629117lja.218.1599227844699; Fri, 04 Sep 2020 06:57:24 -0700 (PDT) MIME-Version: 1.0 References: <20200903144028.20416-1-matthias.schiffer@ew.tq-group.com> In-Reply-To: From: Fabio Estevam Date: Fri, 4 Sep 2020 10:57:13 -0300 Message-ID: Subject: Re: (EXT) Re: [PATCH] spi-imx: remove num-cs support, set num_chipselect to 4 To: Matthias Schiffer Cc: Mark Brown , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-spi , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-kernel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 4, 2020 at 10:02 AM Matthias Schiffer wrote: > This would make num_chipselect default to 1 again (set by > __spi_alloc_controller()), breaking every i.MX board that uses more > than 1 native CS. Which boards are that? Are you referring to non-DT i.MX boards? If so, I have sent a patch removing all non-DT i.MX boards. > I'm aware that using cs-gpios instead of native CS is probably a good > idea in any case, as the native CS of this SPI controller is kinda > flaky (and at a glance it looks like all in-tree DTs do this; not sure > about board files that don't use DTs?), but I'm not convinced that > breaking native CS support completely is desirable either. Initial i.MX chips with this SPI IP had issues in using chip-select in native mode and GPIO chip-select has been used since them. Do we have i.MX dts that make use of native chip select?