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[23.128.96.18]) by mx.google.com with ESMTP id n8si4250298ejj.649.2020.09.04.07.58.02; Fri, 04 Sep 2020 07:58:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=axFOgXNU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730829AbgIDOyQ (ORCPT + 99 others); Fri, 4 Sep 2020 10:54:16 -0400 Received: from mail.kernel.org ([198.145.29.99]:48964 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730815AbgIDOyO (ORCPT ); Fri, 4 Sep 2020 10:54:14 -0400 Received: from kozik-lap.mshome.net (unknown [194.230.155.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 00E3520770; Fri, 4 Sep 2020 14:54:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1599231253; bh=8DCiIQT4QmRUyZL55BGyuiFf/ASSh3pGLjvV3qU7b0U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=axFOgXNUlouJbYTWKptFbEYpVM/XPIw17xVMzEkB/rDE3QaswnNrTWVqeJStS7myj Nex7r/CMeN+JhTLXeHLn4W43h1GVzGeTJcqIsycgfXIEBZIVuYfCNIYpTILSvIJu/u 1PMWepaBkTIANHbg0ODfKbitQhS7xKUfin3fS0b8= From: Krzysztof Kozlowski To: Rob Herring , David Airlie , Daniel Vetter , Lucas Stach , Russell King , Christian Gmeiner , Lee Jones , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Sam Ravnborg , Li Yang , Robert Chiras , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, etnaviv@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Cc: Krzysztof Kozlowski Subject: [PATCH 09/13] arm64: dts: imx8mp-evk: Align pin configuration group names with schema Date: Fri, 4 Sep 2020 16:53:08 +0200 Message-Id: <20200904145312.10960-10-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200904145312.10960-1-krzk@kernel.org> References: <20200904145312.10960-1-krzk@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... 'usdhc3grp-100mhz', 'usdhc3grp-200mhz' do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 3d535f1b3440..ad66f1286d95 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -157,7 +157,7 @@ >; }; - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 >; @@ -182,7 +182,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 @@ -194,7 +194,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 @@ -206,7 +206,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grp-gpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 >; @@ -228,7 +228,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 @@ -244,7 +244,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 -- 2.17.1