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[23.128.96.18]) by mx.google.com with ESMTP id s5si9413573eji.321.2020.09.07.03.45.59; Mon, 07 Sep 2020 03:46:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=8bytes.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728589AbgIGKox (ORCPT + 99 others); Mon, 7 Sep 2020 06:44:53 -0400 Received: from 8bytes.org ([81.169.241.247]:41444 "EHLO theia.8bytes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728791AbgIGKog (ORCPT ); Mon, 7 Sep 2020 06:44:36 -0400 Received: by theia.8bytes.org (Postfix, from userid 1000) id BF8CA34A; Mon, 7 Sep 2020 12:44:33 +0200 (CEST) Date: Mon, 7 Sep 2020 12:44:32 +0200 From: Joerg Roedel To: "Deucher, Alexander" Cc: "jroedel@suse.de" , "Kuehling, Felix" , "iommu@lists.linux-foundation.org" , "Huang, Ray" , "Koenig, Christian" , "Lendacky, Thomas" , "Suthikulpanit, Suravee" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 0/2] iommu/amd: Fix IOMMUv2 devices when SME is active Message-ID: <20200907104431.GH16609@8bytes.org> References: <34db343f-cd23-09af-3bc5-29b9d385f85d@amd.com> <20200828134639.GW3354@suse.de> <60067932-dbf4-d67b-cf11-4dd2b016ed63@amd.com> <20200828152943.GY3354@suse.de> <20200904100556.GU6714@8bytes.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Sep 06, 2020 at 04:08:58PM +0000, Deucher, Alexander wrote: > From f479b9da353c2547c26ebac8930a5dcd9a134eb7 Mon Sep 17 00:00:00 2001 > From: Alex Deucher > Date: Sun, 6 Sep 2020 12:05:12 -0400 > Subject: [PATCH] drm/amdgpu: Fail to load on RAVEN if SME is active > > Due to hardware bugs, scatter/gather display on raven requires > a 1:1 IOMMU mapping, however, SME (System Memory Encryption) > requires an indirect IOMMU mapping because the encryption bit > is beyond the DMA mask of the chip. As such, the two are > incompatible. > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > index 12e16445df7c..d87d37c25329 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -1102,6 +1102,16 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, > return -ENODEV; > } > > + /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, > + * however, SME requires an indirect IOMMU mapping because the encryption > + * bit is beyond the DMA mask of the chip. > + */ > + if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { > + dev_info(&pdev->dev, > + "SME is not compatible with RAVEN\n"); > + return -ENOTSUPP; > + } > + > #ifdef CONFIG_DRM_AMDGPU_SI > if (!amdgpu_si_support) { > switch (flags & AMD_ASIC_MASK) { > -- > 2.25.4 > Looks good to me, thanks. Acked-by: Joerg Roedel