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[23.128.96.18]) by mx.google.com with ESMTP id g11si9700956edy.476.2020.09.07.09.17.58; Mon, 07 Sep 2020 09:18:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730350AbgIGQRJ (ORCPT + 99 others); Mon, 7 Sep 2020 12:17:09 -0400 Received: from foss.arm.com ([217.140.110.172]:40042 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729973AbgIGQQg (ORCPT ); Mon, 7 Sep 2020 12:16:36 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2845831B; Mon, 7 Sep 2020 09:16:29 -0700 (PDT) Received: from e121166-lin.cambridge.arm.com (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0DBE93F68F; Mon, 7 Sep 2020 09:16:27 -0700 (PDT) Date: Mon, 7 Sep 2020 17:16:25 +0100 From: Lorenzo Pieralisi To: Mark Tomlinson Cc: ray.jui@broadcom.com, helgaas@kernel.org, sbranden@broadcom.com, f.fainelli@gmail.com, robh@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/2] PCI: iproc: Set affinity mask on MSI interrupts Message-ID: <20200907161625.GB10272@e121166-lin.cambridge.arm.com> References: <20200803035241.7737-1-mark.tomlinson@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200803035241.7737-1-mark.tomlinson@alliedtelesis.co.nz> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 03, 2020 at 03:52:40PM +1200, Mark Tomlinson wrote: > The core interrupt code expects the irq_set_affinity call to update the > effective affinity for the interrupt. This was not being done, so update > iproc_msi_irq_set_affinity() to do so. > > Fixes: 3bc2b2348835 ("PCI: iproc: Add iProc PCIe MSI support") > Signed-off-by: Mark Tomlinson > --- > changes in v2: > - Patch 1/2 Added Fixes tag > - Patch 2/2 Replace original change with change suggested by Bjorn > Helgaas. > > changes in v3: > - Use bitfield rather than bool to save memory. > > drivers/pci/controller/pcie-iproc-msi.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) Applied to pci/qcom, thanks. Lorenzo > diff --git a/drivers/pci/controller/pcie-iproc-msi.c b/drivers/pci/controller/pcie-iproc-msi.c > index 3176ad3ab0e5..908475d27e0e 100644 > --- a/drivers/pci/controller/pcie-iproc-msi.c > +++ b/drivers/pci/controller/pcie-iproc-msi.c > @@ -209,15 +209,20 @@ static int iproc_msi_irq_set_affinity(struct irq_data *data, > struct iproc_msi *msi = irq_data_get_irq_chip_data(data); > int target_cpu = cpumask_first(mask); > int curr_cpu; > + int ret; > > curr_cpu = hwirq_to_cpu(msi, data->hwirq); > if (curr_cpu == target_cpu) > - return IRQ_SET_MASK_OK_DONE; > + ret = IRQ_SET_MASK_OK_DONE; > + else { > + /* steer MSI to the target CPU */ > + data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu; > + ret = IRQ_SET_MASK_OK; > + } > > - /* steer MSI to the target CPU */ > - data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu; > + irq_data_update_effective_affinity(data, cpumask_of(target_cpu)); > > - return IRQ_SET_MASK_OK; > + return ret; > } > > static void iproc_msi_irq_compose_msi_msg(struct irq_data *data, > -- > 2.28.0 >