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[23.128.96.18]) by mx.google.com with ESMTP id w12si12369500edi.441.2020.09.08.07.26.02; Tue, 08 Sep 2020 07:26:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=2JBREKU6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729337AbgIHOXQ (ORCPT + 99 others); Tue, 8 Sep 2020 10:23:16 -0400 Received: from mail.kernel.org ([198.145.29.99]:37212 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729719AbgIHOPu (ORCPT ); Tue, 8 Sep 2020 10:15:50 -0400 Received: from mail-ua1-f42.google.com (mail-ua1-f42.google.com [209.85.222.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8A2A721D94 for ; Tue, 8 Sep 2020 12:10:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1599567012; bh=lq9eTjrWEGZEa2yiJKmSBpUchaqnuHBGfVpng6L9Aqc=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=2JBREKU6JRgGxsJ1r8Ce2Iju6vIu8ns/qPUApwNkh+GlxhyVWmZki8K1pkhPaBIMI oIjpxoan1Owvg0lws/TNOUleSTdKu7+AxYmUfIWC1QVQyHVnrSntCmcm31oOP9BeIn XhujwMCmWKaMS2a2Z8abpw9lH+pT866FkY6uho3Y= Received: by mail-ua1-f42.google.com with SMTP id z12so4963351uam.12 for ; Tue, 08 Sep 2020 05:10:12 -0700 (PDT) X-Gm-Message-State: AOAM532CwOh3a4SHaXB03We7EThoQCrUFIk4pjrUMW+t2UZ/Hd5Q+mnH 9MZmPpO5YiLp/AE7SMZGDg9hjeUIFw31aLhM4fgW8g== X-Received: by 2002:ab0:384a:: with SMTP id h10mr5065875uaw.77.1599567011727; Tue, 08 Sep 2020 05:10:11 -0700 (PDT) MIME-Version: 1.0 References: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> <20200908075716.30357-7-manivannan.sadhasivam@linaro.org> In-Reply-To: <20200908075716.30357-7-manivannan.sadhasivam@linaro.org> From: Amit Kucheria Date: Tue, 8 Sep 2020 17:40:00 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 6/7] cpufreq: qcom-hw: Add cpufreq support for SM8250 SoC To: Manivannan Sadhasivam Cc: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Andy Gross , Bjorn Andersson , Linux PM list , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , linux-arm-msm , Dmitry Baryshkov , Taniya Das Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 8, 2020 at 1:27 PM Manivannan Sadhasivam wrote: > > SM8250 SoC uses EPSS block for carrying out the cpufreq duties. Hence, add > support for it in the driver with relevant of_match data. > > Signed-off-by: Manivannan Sadhasivam Reviewed-by: Amit Kucheria > --- > drivers/cpufreq/qcom-cpufreq-hw.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c > index de816bcafd33..c3c397cc3dc6 100644 > --- a/drivers/cpufreq/qcom-cpufreq-hw.c > +++ b/drivers/cpufreq/qcom-cpufreq-hw.c > @@ -285,8 +285,17 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { > .lut_row_size = 32, > }; > > +static const struct qcom_cpufreq_soc_data sm8250_soc_data = { > + .reg_enable = 0x0, > + .reg_freq_lut = 0x100, > + .reg_volt_lut = 0x200, > + .reg_perf_state = 0x320, > + .lut_row_size = 4, > +}; > + > static const struct of_device_id qcom_cpufreq_hw_match[] = { > { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, > + { .compatible = "qcom,sm8250-epss", .data = &sm8250_soc_data }, > {} > }; > MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); > -- > 2.17.1 >