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From:   Andy Lutomirski <luto@amacapital.net>
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Subject: Re: [PATCH] x86/msr: do not warn on writes to OC_MAILBOX
Date:   Tue, 8 Sep 2020 13:35:18 -0700
Message-Id: <025308CD-6E1A-41E1-8B3D-E9842CE00794@amacapital.net>
References: <20200908193029.GM25236@zn.tnic>
Cc:     Sultan Alsawaf <sultan@kerneltoast.com>,
        "Jason A. Donenfeld" <Jason@zx2c4.com>,
        Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
        kitsunyan <kitsunyan@airmail.cc>,
        "Brown, Len" <len.brown@intel.com>, X86 ML <x86@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Linus Torvalds <torvalds@linux-foundation.org>
In-Reply-To: <20200908193029.GM25236@zn.tnic>
To:     Borislav Petkov <bp@alien8.de>, Matthew Garrett <mjg59@google.com>,
        James Bottomley <James.Bottomley@hansenpartnership.com>
Sender: linux-kernel-owner@vger.kernel.org
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> On Sep 8, 2020, at 12:30 PM, Borislav Petkov <bp@alien8.de> wrote:
>=20
> =EF=BB=BFOn Tue, Sep 08, 2020 at 12:18:38PM -0700, Sultan Alsawaf wrote:
>> I'd like to point out that on Intel's recent 14nm parts, undervolting
>> is not so much for squeezing every last drop of performance out of the
>> SoC as it is for necessity.
>=20
> <snip interesting examples>
>=20
> Sounds to me that this undervolting functionality should be part of
> the kernel and happen automatically. I have no clue, though, whether
> people who do it, just get lucky and undervolting doesn't cause any
> other hardware issues, or there's a real reason for this power madness
> and if not done, power-related failures happen only on some boxes so
> they decided to do them on all.
>=20
> Or maybe BIOS is nuts, which is not a stretch.
>=20
> Srinivas, what's the story here?
>=20

I have seriously mixed opinions about this.

First, there are really two separate issues here. One is undervolting these p=
arts, and one is the MSR interface.

In my mind, the MSR part is an easy call. Userspace has no more business pok=
ing some undocumented mailbox MSR than it does poking any other MSR. We shou=
ld not give special dispensation here. It should be allowed if the MSR restr=
ictions are off, and otherwise we should warn or forbid it.

Undervolting is a bit different. It=E2=80=99s a genuinely useful configurati=
on that can affect system stability.  In general, I think it should be allow=
ed, and it should have a real driver in tree.

But this has a tricky interaction with lockdown.  An interface that allows r=
oot to destabilize a system may well allow root to escalate privileges.  But=
 I think that making lockdown=3Dintegrity prevent tuning voltages and such w=
ould be quite obnoxious.

Should there perhaps be a separate lockdown bit for stability?

I assume that Intel XTU and such work on Secure-Booted Windows.=