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Date:   Tue, 8 Sep 2020 17:05:20 -0600
From:   Rob Herring <robh@kernel.org>
To:     Manish Narani <manish.narani@xilinx.com>
Cc:     gregkh@linuxfoundation.org, michal.simek@xilinx.com,
        balbi@kernel.org, p.zabel@pengutronix.de,
        linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        git@xilinx.com
Subject: Re: [PATCH 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for
 Versal DWC3 Controller
Message-ID: <20200908230520.GA1102401@bogus>
References: <1598467441-124203-1-git-send-email-manish.narani@xilinx.com>
 <1598467441-124203-2-git-send-email-manish.narani@xilinx.com>
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On Thu, Aug 27, 2020 at 12:14:00AM +0530, Manish Narani wrote:
> Add documentation for Versal DWC3 controller. Add required property
> 'reg' for the same. Also add optional properties for snps,dwc3.
> 
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> ---
>  .../devicetree/bindings/usb/dwc3-xilinx.txt          | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
> index 4aae5b2cef56..dd41ed831411 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
> @@ -1,7 +1,8 @@
>  Xilinx SuperSpeed DWC3 USB SoC controller
>  
>  Required properties:
> -- compatible:	Should contain "xlnx,zynqmp-dwc3"
> +- compatible:	May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
> +- reg:		Base address and length of the register control block
>  - clocks:	A list of phandles for the clocks listed in clock-names
>  - clock-names:	Should contain the following:
>    "bus_clk"	 Master/Core clock, have to be >= 125 MHz for SS
> @@ -13,12 +14,19 @@ Required child node:
>  A child node must exist to represent the core DWC3 IP block. The name of
>  the node is not important. The content of the node is defined in dwc3.txt.
>  
> +Optional properties for snps,dwc3:
> +- dma-coherent:	Enable this flag if CCI is enabled in design. Adding this
> +		flag configures Global SoC bus Configuration Register and
> +		Xilinx USB 3.0 IP - USB coherency register to enable CCI.
> +- interrupt-names: This property provides the names of the interrupt ids used

You have to define what the names are. 'dwc_usb3' seems pretty pointless 
if only 1 name.

> +
>  Example device node:
>  
>  		usb@0 {
>  			#address-cells = <0x2>;
>  			#size-cells = <0x1>;
>  			compatible = "xlnx,zynqmp-dwc3";
> +			reg = <0x0 0xff9d0000 0x0 0x100>;
>  			clock-names = "bus_clk" "ref_clk";
>  			clocks = <&clk125>, <&clk125>;
>  			ranges;
> @@ -26,7 +34,9 @@ Example device node:
>  			dwc3@fe200000 {
>  				compatible = "snps,dwc3";
>  				reg = <0x0 0xfe200000 0x40000>;
> +				interrupt-name = "dwc_usb3";
>  				interrupts = <0x0 0x41 0x4>;
>  				dr_mode = "host";
> +				dma-coherent;
>  			};
>  		};
> -- 
> 2.17.1
>