Received: by 2002:a05:6a10:22f:0:0:0:0 with SMTP id 15csp496592pxk; Wed, 9 Sep 2020 10:39:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9WOO6IDd7BzvpZcKjFhcu3CAKWRr9G8e2co8FAazOVCWBylkeAFhRiFCvQiM93B0P0AYi X-Received: by 2002:a17:906:6007:: with SMTP id o7mr4987058ejj.550.1599673149232; Wed, 09 Sep 2020 10:39:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599673149; cv=none; d=google.com; s=arc-20160816; b=kRDozSlmEsezTAbUmyiWDtzJDYp6QOnBwe/YknGz3ZCWa6yZ+PveOuK3/h3d9dQYQF sammls1ChA27L3v+i2hbGSR5u4y94//aRRi/vSw/yfbpSY1djB8mij9FDaiL4CXWAVUP LOCR1l1x3fkqC2e06zwA81Ejh58muZRpOqVL/WHE146rUzjDug2ZPva2GpAybsn0eu1V bsaK2XZTEMXwkPaF3OS71UuJ8EFgHc9Bt3zOaZNOSnApF0MHLNK+4VLVTFvCDuQ4hDK9 HqSfi7/RfUg7OezB5PU35Ez/1St0fI4bwtUic0fBsbgqYXHQEpvrjkGGhSMTW3+evX6e 9M5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=4REtDRRiq/9VBrmIZ0w14ZdqXSXA1GpKvcCGdlUqRNA=; b=BSspYUbwWzjLHN3Rm9F4KdmWh7haRkczJXBU+7kGIWa9qyHA7qtawn8EhIZ2jCXdsx uDAAh84R4nqPZAPm/l/B8PfkQPX0EkWyY1Xl/HQM1etJ9n35o2b27/xP99NrVzcGO19R k04CkjJ9y6hPeHTds5zkSCxeTDcmkCqn5uVIj/8yZrF4s1/W/+fH/v9HT7+nb/32HHT9 qx89qbdPpPRT0kac8vSv/lRcJJ79P6jqj4WEXjbfL7kiFy4M96KOsUwbBtP56xeR6+z8 r90muWmGqcidt0PbDUG5mNAcPifoZ4dyyCqhv6yCSYD+jdRwAkKqkXkn3eLXK3aUC7Jy UsAg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ml23si1868713ejb.242.2020.09.09.10.38.45; Wed, 09 Sep 2020 10:39:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729822AbgIIRiE (ORCPT + 99 others); Wed, 9 Sep 2020 13:38:04 -0400 Received: from foss.arm.com ([217.140.110.172]:45962 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727856AbgIIRh5 (ORCPT ); Wed, 9 Sep 2020 13:37:57 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D80F0101E; Wed, 9 Sep 2020 10:37:56 -0700 (PDT) Received: from e121166-lin.cambridge.arm.com (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A28B23F68F; Wed, 9 Sep 2020 10:37:55 -0700 (PDT) Date: Wed, 9 Sep 2020 18:37:49 +0100 From: Lorenzo Pieralisi To: Catalin Marinas Cc: George Cherian , Yang Yingliang , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "will.deacon@arm.com" , "bhelgaas@google.com" , "guohanjun@huawei.com" Subject: Re: [PATCH] arm64: PCI: fix memleak when calling pci_iomap/unmap() Message-ID: <20200909173749.GA11781@e121166-lin.cambridge.arm.com> References: <20200907104546.GC26513@gaia> <20200907112118.GD26513@gaia> <20200909113613.GB6384@e121166-lin.cambridge.arm.com> <20200909135400.GB13047@gaia> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200909135400.GB13047@gaia> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 09, 2020 at 02:54:01PM +0100, Catalin Marinas wrote: > On Wed, Sep 09, 2020 at 12:36:13PM +0100, Lorenzo Pieralisi wrote: > > On Mon, Sep 07, 2020 at 12:21:19PM +0100, Catalin Marinas wrote: > > > On Mon, Sep 07, 2020 at 10:51:21AM +0000, George Cherian wrote: > > > > Catalin Marinas wrote: > > > > > On Sat, Sep 05, 2020 at 10:48:11AM +0800, Yang Yingliang wrote: > > > > > > diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index > > > > > > 1006ed2d7c604..ddfa1c53def48 100644 > > > > > > --- a/arch/arm64/kernel/pci.c > > > > > > +++ b/arch/arm64/kernel/pci.c > > > > > > @@ -217,4 +217,9 @@ void pcibios_remove_bus(struct pci_bus *bus) > > > > > > acpi_pci_remove_bus(bus); > > > > > > } > > > > > > > > > > > > +void pci_iounmap(struct pci_dev *dev, void __iomem *addr) { > > > > > > + iounmap(addr); > > > > > > +} > > > > > > +EXPORT_SYMBOL(pci_iounmap); > > > > > > > > > > So, what's wrong with the generic pci_iounmap() implementation? > > > > > Shouldn't it call iounmap() already? > > > > > > > > Since ARM64 selects CONFIG_GENERIC_PCI_IOMAP and not > > > > CONFIG_GENERIC_IOMAP, the pci_iounmap function is reduced to a NULL > > > > function. Due to this, even the managed release variants or even the explicit > > > > pci_iounmap calls doesn't really remove the mappings leading to leak. > > > > > > Ah, I missed the fact that pci_iounmap() depends on a different > > > config option. > > > > > > > https://lkml.org/lkml/2020/8/20/28 > > > > > > So is this going to be fixed in the generic code? That would be my > > > preference. > > > > > > A problem with the iounmap() in the proposed patch is that the region > > > may have been an I/O port, so we could end up unmapping the I/O space. > > > > It boils down to finding a way to match a VA to a BAR resource so that > > we can mirror on pci_iounmap() what's done in pci_iomap_range() (ie > > check BAR resource flags to define how/if to unmap them), that would do > > as a generic pci_iounmap() implementation. > > In the !CONFIG_GENERIC_IOMAP case (arm64), for IORESOURCE_IO, > pci_iomap_range() calls __pci_ioport_map() which, with the default > ioport_map(), it ends up with a simple PCI_IOBASE + (port & > IO_SPACE_LIMIT). > > pci_iounmap() could check whether the pointer is in the PCI_IOBASE - > PCI_IOBASE+IO_SPACE_LIMIT range before calling ioremap(), unless the > arch code re-defined ioport_map. Something like below (not even > compiled): I gave it some thought - with the current state of affairs (which is not ideal - this *_IOMAP stuff is ways too complex) it is likely to be the safest/only way we can have this in generic code, short of implementing what I mentioned (but that implies keeping track of BAR VA mappings) or cleaning up this nest of defines. Lorenzo > diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h > index dabf8cb7203b..fada420c9cd6 100644 > --- a/include/asm-generic/io.h > +++ b/include/asm-generic/io.h > @@ -919,6 +919,11 @@ extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); > #define pci_iounmap pci_iounmap > static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) > { > +#ifndef ARCH_HAS_IOPORT_MAP > + if (p >= PCI_IOBASE && p < PCI_IOBASE + IO_SPACE_LIMIT) > + return; > + iounmap(p); > +#endif > } > #endif > #endif /* CONFIG_GENERIC_IOMAP */ > @@ -1009,7 +1014,9 @@ static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size) > > #ifdef CONFIG_HAS_IOPORT_MAP > #ifndef CONFIG_GENERIC_IOMAP > -#ifndef ioport_map > +#ifdef ioport_map > +#define ARCH_HAS_IOPORT_MAP > +#else > #define ioport_map ioport_map > static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) > { > > -- > Catalin