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[23.128.96.18]) by mx.google.com with ESMTP id c2si2002848ejx.46.2020.09.09.11.23.44; Wed, 09 Sep 2020 11:24:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=y9d+1uXi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729824AbgIISUi (ORCPT + 99 others); Wed, 9 Sep 2020 14:20:38 -0400 Received: from mail.kernel.org ([198.145.29.99]:35776 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725772AbgIISUf (ORCPT ); Wed, 9 Sep 2020 14:20:35 -0400 Received: from mail-oo1-f42.google.com (mail-oo1-f42.google.com [209.85.161.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 272A721D7F; Wed, 9 Sep 2020 18:20:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1599675634; bh=JaN9N3pcoNDn3owpWWs48WvhhA1KCzxeHdaE/iRZjgY=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=y9d+1uXio6dNOyfxskd1CxCQ+TgygEg+TrXynmG2dimfIx0KVIbsAGTMnEIV9+RPv 2dv3e306tPEquqIstAJkY9BiBdbcHvYCSZZ/rZfcdUT/449LRkS5bG0K0C89CGRQjH OL8p/S2idASTo/qcXlpkEsmrOwhkLb2HooWYjisA= Received: by mail-oo1-f42.google.com with SMTP id m25so809195oou.0; Wed, 09 Sep 2020 11:20:34 -0700 (PDT) X-Gm-Message-State: AOAM532cDOpxBx4SSLcnmhtT1LD6iVYgYB6JTc+6Uh6rCK/z1oGlc1fW BcEhcWEZQFyzZjqRUtr2pYrHty8NrB/NC7pHeA== X-Received: by 2002:a4a:d306:: with SMTP id g6mr1662606oos.25.1599675633402; Wed, 09 Sep 2020 11:20:33 -0700 (PDT) MIME-Version: 1.0 References: <20200817030324.5690-1-crystal.guo@mediatek.com> <20200817030324.5690-3-crystal.guo@mediatek.com> <20200825190219.GA1125997@bogus> <1598440183.30048.14.camel@mhfsdcap03> <6c292056-1cb1-bc6c-0422-46e047dcf08f@ti.com> In-Reply-To: From: Rob Herring Date: Wed, 9 Sep 2020 12:20:21 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [v4,2/4] dt-binding: reset-controller: ti: add 'mediatek,infra-reset' to compatible To: Suman Anna Cc: Crystal Guo , "p.zabel@pengutronix.de" , "matthias.bgg@gmail.com" , srv_heupstream , "linux-mediatek@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , =?UTF-8?B?U2VpeWEgV2FuZyAo546L6L+65ZCbKQ==?= , =?UTF-8?B?U3RhbmxleSBDaHUgKOacseWOn+mZnik=?= , =?UTF-8?B?WWluZ2pvZSBDaGVuICjpmbPoi7HmtLIp?= , =?UTF-8?B?RmFuIENoZW4gKOmZs+WHoSk=?= , =?UTF-8?B?WW9uZyBMaWFuZyAo5qKB5YuHKQ==?= Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 9, 2020 at 9:10 AM Suman Anna wrote: > > On 9/8/20 1:49 PM, Rob Herring wrote: > > On Wed, Sep 2, 2020 at 5:26 PM Suman Anna wrote: > >> > >> Hi Rob, > >> > >> On 8/26/20 6:09 AM, Crystal Guo wrote: > >>> On Wed, 2020-08-26 at 03:02 +0800, Rob Herring wrote: > >>>> On Mon, Aug 17, 2020 at 11:03:22AM +0800, Crystal Guo wrote: > >>>>> The TI syscon reset controller provides a common reset management, > >>>>> and is suitable for MTK SoCs. Add compatible 'mediatek,infra-reset', > >>>>> which denotes to use ti reset-controller driver directly. > >>>>> > >>>>> Signed-off-by: Crystal Guo > >>>>> --- > >>>>> Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 1 + > >>>>> 1 file changed, 1 insertion(+) > >>>>> > >>>>> diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt > >>>>> index ab041032339b..5a0e9365b51b 100644 > >>>>> --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt > >>>>> +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt > >>>>> @@ -25,6 +25,7 @@ Required properties: > >>>>> "ti,k2l-pscrst" > >>>>> "ti,k2hk-pscrst" > >>>>> "ti,syscon-reset" > >>>>> + "mediatek,infra-reset", "ti,syscon-reset" > >>>> > >>>> You need your own binding doc. If you can use the same driver then fine, > >>>> but that's a separate issue. There's also reset-simple driver if you > >>>> have just array of 32-bit registers with a bit per reset. > >>>> > >>>> Don't repeat 'ti,reset-bits' either. > >>> > >>> Do you mean I should add a Mediatek reset binding doc, although Mediatek > >>> reuse the TI reset controller directly? > >> > >> Hmm, how do you envision not repeating the same bits in a separate binding? > > > > I mean 'ti,reset-bits' isn't really something that should have been in > > DT in the first place, but rather implied by the compatible string. > > Ok, should I be deprecating this and move this data to driver then? No, I'm just asking to not have new users. > I am assuming that is how you are envisioning the new Mediatek binding to be > atleast. Right. Rob