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Wed, 9 Sep 2020 13:44:54 -0700 Received: from [10.18.5.8] (helo=xsjamitsuni51.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1kG6xa-0007dJ-8c; Wed, 09 Sep 2020 13:44:54 -0700 From: Amit Sunil Dhamne To: mturquette@baylibre.com, m.tretter@pengutronix.de, sboyd@kernel.org, michal.simek@xilinx.com, mark.rutland@arm.com, linux-clk@vger.kernel.org Cc: rajanv@xilinx.com, jollys@xilinx.com, tejasp@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rajan Vaja , Tejas Patel , Amit Sunil Dhamne Subject: [PATCH v4 1/3] clk: zynqmp: Use firmware specific common clock flags Date: Wed, 9 Sep 2020 13:44:46 -0700 Message-Id: <1599684288-20917-2-git-send-email-amit.sunil.dhamne@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599684288-20917-1-git-send-email-amit.sunil.dhamne@xilinx.com> References: <1599684288-20917-1-git-send-email-amit.sunil.dhamne@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: e125bc2e-b1e0-4412-f211-08d855013851 X-MS-TrafficTypeDiagnostic: SN6PR02MB5102: X-Microsoft-Antispam-PRVS: Content-Transfer-Encoding: quoted-printable X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3631; 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So firmware needs to be updated if CCF flags are changed. The firmware should have its own 'flag number space' that is distinct from the common clk framework's 'flag number space'. So define and use ZynqMP specific common clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja Signed-off-by: Tejas Patel Signed-off-by: Amit Sunil Dhamne --- drivers/clk/zynqmp/clk-gate-zynqmp.c | 4 +++- drivers/clk/zynqmp/clk-mux-zynqmp.c | 4 +++- drivers/clk/zynqmp/clk-zynqmp.h | 24 ++++++++++++++++++++++++ drivers/clk/zynqmp/clkc.c | 33 ++++++++++++++++++++++++++++++++= - drivers/clk/zynqmp/divider.c | 5 +++-- drivers/clk/zynqmp/pll.c | 4 +++- 6 files changed, 68 insertions(+), 6 deletions(-) diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-= gate-zynqmp.c index 10c9b88..695feaa 100644 --- a/drivers/clk/zynqmp/clk-gate-zynqmp.c +++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c @@ -121,7 +121,9 @@ struct clk_hw *zynqmp_clk_register_gate(const char *nam= e, u32 clk_id, init.name =3D name; init.ops =3D &zynqmp_clk_gate_ops; - init.flags =3D nodes->flag; + + init.flags =3D zynqmp_clk_map_common_ccf_flags(nodes->flag); + init.parent_names =3D parents; init.num_parents =3D 1; diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-m= ux-zynqmp.c index 0619414..a49b1c5 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -120,7 +120,9 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name= , u32 clk_id, init.ops =3D &zynqmp_clk_mux_ro_ops; else init.ops =3D &zynqmp_clk_mux_ops; - init.flags =3D nodes->flag; + + init.flags =3D zynqmp_clk_map_common_ccf_flags(nodes->flag); + init.parent_names =3D parents; init.num_parents =3D num_parents; mux->flags =3D nodes->type_flag; diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqm= p.h index 5beeb41..974d3da 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -10,6 +10,28 @@ #include +/* Common Flags */ +/* must be gated across rate change */ +#define ZYNQMP_CLK_SET_RATE_GATE BIT(0) +/* must be gated across re-parent */ +#define ZYNQMP_CLK_SET_PARENT_GATE BIT(1) +/* propagate rate change up one level */ +#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2) +/* do not gate even if unused */ +#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3) +/* do not use the cached clk rate */ +#define ZYNQMP_CLK_GET_RATE_NOCACHE BIT(6) +/* don't re-parent on rate change */ +#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7) +/* do not use the cached clk accuracy */ +#define ZYNQMP_CLK_GET_ACCURACY_NOCACHE BIT(8) +/* recalc rates after notifications */ +#define ZYNQMP_CLK_RECALC_NEW_RATES BIT(9) +/* clock needs to run to set rate */ +#define ZYNQMP_CLK_SET_RATE_UNGATE BIT(10) +/* do not gate, ever */ +#define ZYNQMP_CLK_IS_CRITICAL BIT(11) + enum topology_type { TYPE_INVALID, TYPE_MUX, @@ -33,6 +55,8 @@ struct clock_topology { u8 custom_type_flag; }; +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag); + struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, const char * const *parents, u8 num_parents, diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c index db8d0d7..af06a19 100644 --- a/drivers/clk/zynqmp/clkc.c +++ b/drivers/clk/zynqmp/clkc.c @@ -271,6 +271,34 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, = u32 index, return ret; } +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag) +{ + unsigned long ccf_flag =3D 0; + + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE) + ccf_flag |=3D CLK_SET_RATE_GATE; + if (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE) + ccf_flag |=3D CLK_SET_PARENT_GATE; + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT) + ccf_flag |=3D CLK_SET_RATE_PARENT; + if (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED) + ccf_flag |=3D CLK_IGNORE_UNUSED; + if (zynqmp_flag & ZYNQMP_CLK_GET_RATE_NOCACHE) + ccf_flag |=3D CLK_GET_RATE_NOCACHE; + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT) + ccf_flag |=3D CLK_SET_RATE_NO_REPARENT; + if (zynqmp_flag & ZYNQMP_CLK_GET_ACCURACY_NOCACHE) + ccf_flag |=3D CLK_GET_ACCURACY_NOCACHE; + if (zynqmp_flag & ZYNQMP_CLK_RECALC_NEW_RATES) + ccf_flag |=3D CLK_RECALC_NEW_RATES; + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_UNGATE) + ccf_flag |=3D CLK_SET_RATE_UNGATE; + if (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL) + ccf_flag |=3D CLK_IS_CRITICAL; + + return ccf_flag; +} + /** * zynqmp_clk_register_fixed_factor() - Register fixed factor with the * clock framework @@ -292,6 +320,7 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const c= har *name, u32 clk_id, struct zynqmp_pm_query_data qdata =3D {0}; u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; + unsigned long flag; qdata.qid =3D PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS; qdata.arg1 =3D clk_id; @@ -303,9 +332,11 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const = char *name, u32 clk_id, mult =3D ret_payload[1]; div =3D ret_payload[2]; + flag =3D zynqmp_clk_map_common_ccf_flags(nodes->flag); + hw =3D clk_hw_register_fixed_factor(NULL, name, parents[0], - nodes->flag, mult, + flag, mult, div); return hw; diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 66da02b..775d54f 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -311,8 +311,9 @@ struct clk_hw *zynqmp_clk_register_divider(const char *= name, init.name =3D name; init.ops =3D &zynqmp_clk_divider_ops; - /* CLK_FRAC is not defined in the common clk framework */ - init.flags =3D nodes->flag & ~CLK_FRAC; + + init.flags =3D zynqmp_clk_map_common_ccf_flags(nodes->flag); + init.parent_names =3D parents; init.num_parents =3D 1; diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index 92f449e..d188924 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -302,7 +302,9 @@ struct clk_hw *zynqmp_clk_register_pll(const char *name= , u32 clk_id, init.name =3D name; init.ops =3D &zynqmp_pll_ops; - init.flags =3D nodes->flag; + + init.flags =3D zynqmp_clk_map_common_ccf_flags(nodes->flag); + init.parent_names =3D parents; init.num_parents =3D 1; -- 2.7.4 This email and any attachments are intended for the sole use of the named r= ecipient(s) and contain(s) confidential information that may be proprietary= , privileged or copyrighted under applicable law. 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