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bh=OF9x9aCRYQId9DTEeUUlbYKv+AnvnaiO1HEaClAF3pU=; b=Xb8Y+dLmLVl/zabUA59PyyOneY37HHoEiwTTG+SYvwLhcuR1skaq0fwN5bOpMVW6fv XXNKAZtJKX5IRSWwEYzSUGU3cxfeNYJyXW4PuOVWS1EpUlpasNyoyLuYTBUkxyRKagKY RaEVgITQP21ze+WdEfmn5vwhakcahw6ToK09XoVEexjtpNRC/gcu0Yl0+obdYshs/q5C uv/CINimL14DFFLd+UlmJctnnbOnMfkPz+R1unnmvtJJFlsSFpwVRI5kXHOxXzBxCcs7 R6C0dMJPQo0u9u6V2Tsz5oGQx8HgqPzIc1oLoHATX1Ya6XINKwynqn4oHSN3iRISkpRR 8mfA== X-Gm-Message-State: AOAM532zuGFyBxOHh2meR5FE8v0SigBnar6JQwDgOqZW/XgS0AeYX7yE 1xERQfzUEdveF3sPPMig6GCl5tbTw8w= X-Received: by 2002:a54:4e84:: with SMTP id c4mr586085oiy.22.1599756799753; Thu, 10 Sep 2020 09:53:19 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id b1sm1004074oof.8.2020.09.10.09.53.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Sep 2020 09:53:18 -0700 (PDT) Subject: Re: [PATCH 2/2] watchdog: sp5100_tco: Enable watchdog on Family 17h devices if disabled To: Jan Kiszka , Wim Van Sebroeck Cc: linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org References: <20200910163109.235136-1-linux@roeck-us.net> <20200910163109.235136-2-linux@roeck-us.net> <30f69c2c-d4c8-a143-6bfa-34394b6361cf@siemens.com> From: Guenter Roeck Autocrypt: addr=linux@roeck-us.net; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <30f69c2c-d4c8-a143-6bfa-34394b6361cf@siemens.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jan, On 9/10/20 9:34 AM, Jan Kiszka wrote: > On 10.09.20 18:31, Guenter Roeck wrote: >> On Family 17h (Ryzen) devices, the WatchdogTmrEn bit of PmDecodeEn not only >> enables watchdog memory decoding at 0xfeb00000, it also enables the >> watchdog hardware itself. Use this information to enable the watchdog if >> it is not already enabled. >> >> Cc: Jan Kiszka >> Signed-off-by: Guenter Roeck >> --- >> drivers/watchdog/sp5100_tco.c | 18 ++++++++++++++++++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/drivers/watchdog/sp5100_tco.c b/drivers/watchdog/sp5100_tco.c >> index 85e9664318c9..a730ecbf78cd 100644 >> --- a/drivers/watchdog/sp5100_tco.c >> +++ b/drivers/watchdog/sp5100_tco.c >> @@ -17,6 +17,12 @@ >> * AMD Publication 51192 "AMD Bolton FCH Register Reference Guide" >> * AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG) >> * for AMD Family 16h Models 30h-3Fh Processors" >> + * AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR) >> + * for AMD Family 17h Model 18h, Revision B1 >> + * Processors (PUB) >> + * AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR) >> + * for AMD Family 17h Model 20h, Revision A1 >> + * Processors (PUB) >> */ >> >> /* >> @@ -241,6 +247,18 @@ static int sp5100_tco_setupdevice(struct device *dev, >> break; >> case efch: >> dev_name = SB800_DEVNAME; >> + /* >> + * On Family 17h devices, the EFCH_PM_DECODEEN_WDT_TMREN bit of >> + * EFCH_PM_DECODEEN not only enables the EFCH_PM_WDT_ADDR memory >> + * region, it also enables the watchdog itself. >> + */ >> + if (boot_cpu_data.x86 == 0x17) { >> + val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN); >> + if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) { >> + sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN, 0xff, >> + EFCH_PM_DECODEEN_WDT_TMREN); >> + } >> + } >> val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN); >> if (val & EFCH_PM_DECODEEN_WDT_TMREN) >> mmio_addr = EFCH_PM_WDT_ADDR; >> > > Won't that bring us EFCH_PM_WDT_ADDR as address, rather than > EFCH_PM_ACPI_MMIO_ADDR which worked in my case? Or is one an alias of > the other. > Yes, it does use EFCH_PM_WDT_ADDR. EFCH_PM_ACPI_MMIO_ADDR works as well, but is meant to be a fallback. Both point to the watchdog memory space. Thanks, Guenter