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Subject: Re: [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as
 a CPUID feature
To:     Dave Hansen <dave.hansen@intel.com>, kvm@vger.kernel.org
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        mingo@redhat.com, bp@alien8.de, x86@kernel.org,
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        dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org,
        linux-kernel@vger.kernel.org, hpa@zytor.com
References: <20200911192601.9591-1-krish.sadhukhan@oracle.com>
 <20200911192601.9591-3-krish.sadhukhan@oracle.com>
 <c5cbc91e-f576-5cc7-a40c-c11abaea4ad2@intel.com>
From:   Krish Sadhukhan <krish.sadhukhan@oracle.com>
Message-ID: <472e71a4-e50e-1d39-3088-cc103c79ddb3@oracle.com>
Date:   Fri, 11 Sep 2020 13:10:30 -0700
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On 9/11/20 12:36 PM, Dave Hansen wrote:
> On 9/11/20 12:25 PM, Krish Sadhukhan wrote:
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index 81335e6fe47d..0e5b27ee5931 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -293,6 +293,7 @@
>>   #define X86_FEATURE_FENCE_SWAPGS_USER	(11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
>>   #define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
>>   #define X86_FEATURE_SPLIT_LOCK_DETECT	(11*32+ 6) /* #AC for split lock */
>> +#define X86_FEATURE_HW_CACHE_COHERENCY (11*32+ 7) /* AMD hardware-enforced cache coherency */
> That's an awfully generic name.  We generally have "hardware-enforced
> cache coherency" already everywhere. :)
>
> This probably needs to say something about encryption, or even SEV
> specifically.


How about X86_FEATURE_ENC_CACHE_COHERENCY ?

> I also don't see this bit in the "AMD64 Architecture
> Programmer’s Manual".  Did I look in the wrong spot somehow?
Section 7.10.6 in APM mentions this.