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Subject: Re: [PATCH v1 1/3] clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     David Brown <david.brown@linaro.org>,
        Rajendra Nayak <rnayak@codeaurora.org>,
        linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        Andy Gross <agross@kernel.org>, devicetree@vger.kernel.org,
        robh@kernel.org, robh+dt@kernel.org,
        Taniya Das <tdas@codeaurora.org>
To:     Michael Turquette <mturquette@baylibre.com>,
        Taniya Das <tdas@codeaurora.org>
Date:   Mon, 14 Sep 2020 17:13:46 -0700
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Quoting Taniya Das (2020-09-08 10:07:26)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alph=
a-pll.c
> index 26139ef..fb27fcf 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -1561,3 +1571,75 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_o=
ps =3D {
>         .set_rate =3D clk_alpha_pll_postdiv_fabia_set_rate,
>  };
>  EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
> +
> +void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *r=
egmap,
> +                       const struct alpha_pll_config *config)
> +{
> +       if (config->l)
> +               regmap_write(regmap, PLL_L_VAL(pll), config->l);
> +
> +       if (config->alpha)
> +               regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> +
> +       if (config->user_ctl_val)
> +               regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_=
val);
> +
> +       if (config->config_ctl_val)
> +               regmap_write(regmap, PLL_CONFIG_CTL(pll),
> +                                               config->config_ctl_val);
> +
> +       if (config->config_ctl_hi_val)
> +               regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
> +                                               config->config_ctl_hi_val=
);
> +
> +       if (config->test_ctl_val)
> +               regmap_write(regmap, PLL_TEST_CTL(pll),
> +                                               config->test_ctl_val);
> +
> +       if (config->test_ctl_hi_val)
> +               regmap_write(regmap,  PLL_TEST_CTL_U(pll),
> +                                               config->test_ctl_hi_val);
> +}
> +EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
> +
> +static int alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rat=
e,

Why not clk_alpha_pll prefix? We should prefix the other PLL functions
in here with clk_alpha_ like trion and fabia

> +                                                       unsigned long pra=
te)
> +{
> +       struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw);
> +       u32 l, alpha_width =3D pll_alpha_width(pll);
> +       unsigned long rrate;
> +       u64 a;
> +
> +       rrate =3D alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
> +
> +       /*
> +        * Due to limited number of bits for fractional rate programming,=
 the
> +        * rounded up rate could be marginally higher than the requested =
rate.
> +        */
> +       if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
> +               pr_err("Call set rate on the PLL with rounded rates!\n");
> +               return -EINVAL;
> +       }

See commit f78f29079327 ("clk: qcom: alpha-pll: Make error prints more
informative") where I tried to make this better. Can you extract this
check into a function that helps us understand the error better?

> +
> +       /* change L_VAL without having to go through the power on sequenc=
e */
> +       regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
> +       regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
> +
> +       /* Ensure that the write above goes through before proceeding. */
> +       mb();

regmap has an mb() in it. Remove this?

> +
> +       if (clk_hw_is_enabled(hw))
> +               return wait_for_pll_enable_lock(pll);
> +
> +       return 0;
> +}
> +
> +const struct clk_ops clk_alpha_pll_agera_ops =3D {
> +       .enable =3D clk_alpha_pll_enable,
> +       .disable =3D clk_alpha_pll_disable,
> +       .is_enabled =3D clk_alpha_pll_is_enabled,
> +       .recalc_rate =3D alpha_pll_fabia_recalc_rate,
> +       .round_rate =3D clk_alpha_pll_round_rate,
> +       .set_rate =3D alpha_pll_agera_set_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);