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Tue, 15 Sep 2020 15:12:02 +0000 From: Ming Qiao To: bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ming Qiao , Rajat Jain Subject: [PATCH 3/3] PCI: Add quirks for Juniper ASICs to fix PCIe gen Date: Tue, 15 Sep 2020 08:11:03 -0700 Message-Id: <20200915151103.7086-3-mqiao@juniper.net> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20200915151103.7086-1-mqiao@juniper.net> References: <20200915151103.7086-1-mqiao@juniper.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: BL0PR02CA0086.namprd02.prod.outlook.com (2603:10b6:208:51::27) To BYAPR05MB5592.namprd05.prod.outlook.com (2603:10b6:a03:19::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from qnc-ubm16-mqiao.juniper.net (66.129.224.68) by BL0PR02CA0086.namprd02.prod.outlook.com (2603:10b6:208:51::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3370.16 via Frontend Transport; Tue, 15 Sep 2020 15:12:00 +0000 X-Mailer: git-send-email 2.10.0 X-Originating-IP: [66.129.224.68] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: ae4727c0-8340-4145-d4a9-08d85989b2a4 X-MS-TrafficTypeDiagnostic: BYAPR05MB5589: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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Make the root port to ignore these fields.          Signed-off-by: Rajat Jain Signed-off-by: Ming Qiao --- drivers/pci/quirks.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 04dd490..0a28a09 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5658,6 +5658,45 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00A9, quirk_jnx_fpga); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x00AA, quirk_jnx_fpga); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_XILINX, 0x0505, quirk_jnx_fpga); +static struct dmi_system_id jnx_asic_pci_bug_affected_platforms[] = { + { + .ident = "Juniper Networks PTX MLC Card", + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "Juniper Networks Inc."), + DMI_MATCH(DMI_BOARD_NAME, "0C0A") + }, + }, + {}, +}; +MODULE_DEVICE_TABLE(dmi, jnx_asic_pci_bug_affected_platforms); + +#define INTEL_DEBUG_REG 0x8F8 +#define INTEL_DEBUG_REG_IGNORE_GEN BIT(3) + +/* + * Some Juniper ASICs have an issue where they report incorrect gen type + * (Gen-1 / Gen-2) for the PCIe link to the root port. + * This workaround needs to be applied to each Intel root port which connects + * to such juniper ASIC. It causes the root port to ignore the incorrect + * fields. + */ +static void fixup_jnx_intel_root_port(struct pci_dev *dev) +{ + struct pci_dev *root; + u32 tmp32; + int ret; + + root = pcie_find_root_port(dev); + if (!root || root->vendor != PCI_VENDOR_ID_INTEL) + return; + + ret = pci_read_config_dword(root, INTEL_DEBUG_REG, &tmp32); + tmp32 |= INTEL_DEBUG_REG_IGNORE_GEN; + ret |= pci_write_config_dword(root, INTEL_DEBUG_REG, tmp32); + if (ret) + dev_err(&root->dev, "Failed on root port quirk. CONFIG_PCI_MMCONFIG not selected?\n"); +} + /* * PCI class reported by some Juniper ASICs is not correct. * Change it to NETWORK. @@ -5665,6 +5704,9 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_XILINX, 0x0505, quirk_jnx_fpga); static void quirk_jnx_asic(struct pci_dev *dev) { dev->class = PCI_CLASS_NETWORK_OTHER << 8; + + if (dmi_check_system(jnx_asic_pci_bug_affected_platforms)) + fixup_jnx_intel_root_port(dev) } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x003C, quirk_jnx_asic); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JUNIPER, 0x003D, quirk_jnx_asic); -- 2.10.0