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Subject: Re: [PATCH] dmaengine: ti: k3-udma-glue: fix channel enable functions
To:     Grygorii Strashko <grygorii.strashko@ti.com>,
        Vinod Koul <vkoul@kernel.org>, <dmaengine@vger.kernel.org>
CC:     Sekhar Nori <nsekhar@ti.com>, <linux-kernel@vger.kernel.org>,
        Vignesh Raghavendra <vigneshr@ti.com>
References: <20200915164149.22123-1-grygorii.strashko@ti.com>
From:   Peter Ujfalusi <peter.ujfalusi@ti.com>
Message-ID: <46ea0401-e4f7-5b08-c780-b6cd7d1af5e9@ti.com>
Date:   Wed, 16 Sep 2020 11:35:50 +0300
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On 15/09/2020 19.41, Grygorii Strashko wrote:
> Now the K3 UDMA glue layer enable functions perform RMW operation on UD=
MA
> RX/TX RT_CTL registers to set EN bit and enable channel, which is
> incorrect, because only EN bit has to be set in those registers to enab=
le
> channel (all other bits should be cleared 0).
> More over, this causes issues when bootloader leaves UDMA channel RX/TX=

> RT_CTL registers in incorrect state - TDOWN bit set, for example. As
> result, UDMA channel will just perform teardown right after it's enable=
d.
>=20
> Hence, fix it by writing correct values (EN=3D1) directly in UDMA chann=
el
> RX/TX RT_CTL registers in k3_udma_glue_enable_tx/rx_chn() functions.

This is how the DMAengine driver deals with the enable.

Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

> Fixes: d70241913413 ("dmaengine: ti: k3-udma: Add glue layer for non DM=
Aengine users")
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
> ---
>  drivers/dma/ti/k3-udma-glue.c | 15 +++------------
>  1 file changed, 3 insertions(+), 12 deletions(-)
>=20
> diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glu=
e.c
> index dc03880f021a..37d706cf3ba9 100644
> --- a/drivers/dma/ti/k3-udma-glue.c
> +++ b/drivers/dma/ti/k3-udma-glue.c
> @@ -370,7 +370,6 @@ EXPORT_SYMBOL_GPL(k3_udma_glue_pop_tx_chn);
> =20
>  int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)=

>  {
> -	u32 txrt_ctl;
>  	int ret;
> =20
>  	ret =3D xudma_navss_psil_pair(tx_chn->common.udmax,
> @@ -383,15 +382,11 @@ int k3_udma_glue_enable_tx_chn(struct k3_udma_glu=
e_tx_channel *tx_chn)
> =20
>  	tx_chn->psil_paired =3D true;
> =20
> -	txrt_ctl =3D UDMA_PEER_RT_EN_ENABLE;
>  	xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,=

> -			    txrt_ctl);
> +			    UDMA_PEER_RT_EN_ENABLE);
> =20
> -	txrt_ctl =3D xudma_tchanrt_read(tx_chn->udma_tchanx,
> -				      UDMA_CHAN_RT_CTL_REG);
> -	txrt_ctl |=3D UDMA_CHAN_RT_CTL_EN;
>  	xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
> -			    txrt_ctl);
> +			    UDMA_CHAN_RT_CTL_EN);
> =20
>  	k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en");
>  	return 0;
> @@ -1059,7 +1054,6 @@ EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_disable);
> =20
>  int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)=

>  {
> -	u32 rxrt_ctl;
>  	int ret;
> =20
>  	if (rx_chn->remote)
> @@ -1078,11 +1072,8 @@ int k3_udma_glue_enable_rx_chn(struct k3_udma_gl=
ue_rx_channel *rx_chn)
> =20
>  	rx_chn->psil_paired =3D true;
> =20
> -	rxrt_ctl =3D xudma_rchanrt_read(rx_chn->udma_rchanx,
> -				      UDMA_CHAN_RT_CTL_REG);
> -	rxrt_ctl |=3D UDMA_CHAN_RT_CTL_EN;
>  	xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
> -			    rxrt_ctl);
> +			    UDMA_CHAN_RT_CTL_EN);
> =20
>  	xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,=

>  			    UDMA_PEER_RT_EN_ENABLE);
>=20

- P=C3=A9ter

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