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From:   Joel Stanley <joel@jms.id.au>
Date:   Wed, 16 Sep 2020 13:15:12 +0000
Message-ID: <CACPK8Xfr8KQkKAtxC4FaWk-HKkSvgBnkrpF6yMBT0qxY16zmWQ@mail.gmail.com>
Subject: Re: [PATCH v5 1/3] arm: dts: modify NPCM7xx device tree clock parameter
To:     Tomer Maimon <tmaimon77@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Avi Fishman <avifishman70@gmail.com>,
        Tali Perry <tali.perry1@gmail.com>,
        Patrick Venture <venture@google.com>,
        Nancy Yuen <yuenn@google.com>,
        Benjamin Fair <benjaminfair@google.com>,
        devicetree <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        OpenBMC Maillist <openbmc@lists.ozlabs.org>
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Sender: linux-kernel-owner@vger.kernel.org
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On Wed, 16 Sep 2020 at 12:56, Tomer Maimon <tmaimon77@gmail.com> wrote:
>
> Modify NPCM7xx device tree clock parameter to clock constants that
> define at include/dt-bindings/clock/nuvoton,npcm7xx-clock.h file.
>
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

Reviewed-by: Joel Stanley <joel@jms.id.au>

> ---
>  arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 19 ++++++++++---------
>  arch/arm/boot/dts/nuvoton-npcm750.dtsi        |  6 +++---
>  2 files changed, 13 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> index d2d0761295a4..16a28c5c4131 100644
> --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> @@ -3,6 +3,7 @@
>  // Copyright 2018 Google, Inc.
>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
>
>  / {
>         #address-cells = <1>;
> @@ -80,7 +81,7 @@
>                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>                         cache-unified;
>                         cache-level = <2>;
> -                       clocks = <&clk 10>;
> +                       clocks = <&clk NPCM7XX_CLK_AXI>;
>                         arm,shared-override;
>                 };
>
> @@ -120,7 +121,7 @@
>                                 compatible = "nuvoton,npcm750-timer";
>                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>                                 reg = <0x8000 0x50>;
> -                               clocks = <&clk 5>;
> +                               clocks = <&clk NPCM7XX_CLK_TIMER>;
>                         };
>
>                         watchdog0: watchdog@801C {
> @@ -128,7 +129,7 @@
>                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
>                                 reg = <0x801C 0x4>;
>                                 status = "disabled";
> -                               clocks = <&clk 5>;
> +                               clocks = <&clk NPCM7XX_CLK_TIMER>;
>                         };
>
>                         watchdog1: watchdog@901C {
> @@ -136,7 +137,7 @@
>                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>                                 reg = <0x901C 0x4>;
>                                 status = "disabled";
> -                               clocks = <&clk 5>;
> +                               clocks = <&clk NPCM7XX_CLK_TIMER>;
>                         };
>
>                         watchdog2: watchdog@a01C {
> @@ -144,13 +145,13 @@
>                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
>                                 reg = <0xa01C 0x4>;
>                                 status = "disabled";
> -                               clocks = <&clk 5>;
> +                               clocks = <&clk NPCM7XX_CLK_TIMER>;
>                         };
>
>                         serial0: serial@1000 {
>                                 compatible = "nuvoton,npcm750-uart";
>                                 reg = <0x1000 0x1000>;
> -                               clocks = <&clk 6>;
> +                               clocks = <&clk NPCM7XX_CLK_UART>;
>                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>                                 reg-shift = <2>;
>                                 status = "disabled";
> @@ -159,7 +160,7 @@
>                         serial1: serial@2000 {
>                                 compatible = "nuvoton,npcm750-uart";
>                                 reg = <0x2000 0x1000>;
> -                               clocks = <&clk 6>;
> +                               clocks = <&clk NPCM7XX_CLK_UART>;
>                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>                                 reg-shift = <2>;
>                                 status = "disabled";
> @@ -168,7 +169,7 @@
>                         serial2: serial@3000 {
>                                 compatible = "nuvoton,npcm750-uart";
>                                 reg = <0x3000 0x1000>;
> -                               clocks = <&clk 6>;
> +                               clocks = <&clk NPCM7XX_CLK_UART>;
>                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>                                 reg-shift = <2>;
>                                 status = "disabled";
> @@ -177,7 +178,7 @@
>                         serial3: serial@4000 {
>                                 compatible = "nuvoton,npcm750-uart";
>                                 reg = <0x4000 0x1000>;
> -                               clocks = <&clk 6>;
> +                               clocks = <&clk NPCM7XX_CLK_UART>;
>                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>                                 reg-shift = <2>;
>                                 status = "disabled";
> diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
> index 6ac340533587..a37bb2294b8f 100644
> --- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
> +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
> @@ -17,7 +17,7 @@
>                 cpu@0 {
>                         device_type = "cpu";
>                         compatible = "arm,cortex-a9";
> -                       clocks = <&clk 0>;
> +                       clocks = <&clk NPCM7XX_CLK_CPU>;
>                         clock-names = "clk_cpu";
>                         reg = <0>;
>                         next-level-cache = <&l2>;
> @@ -26,7 +26,7 @@
>                 cpu@1 {
>                         device_type = "cpu";
>                         compatible = "arm,cortex-a9";
> -                       clocks = <&clk 0>;
> +                       clocks = <&clk NPCM7XX_CLK_CPU>;
>                         clock-names = "clk_cpu";
>                         reg = <1>;
>                         next-level-cache = <&l2>;
> @@ -38,7 +38,7 @@
>                         reg = <0x3fe600 0x20>;
>                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
>                                                   IRQ_TYPE_LEVEL_HIGH)>;
> -                       clocks = <&clk 5>;
> +                       clocks = <&clk NPCM7XX_CLK_AHB>;
>                 };
>         };
>  };
> --
> 2.22.0
>