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Date:   Thu, 17 Sep 2020 12:43:15 +0200
From:   Thierry Reding <thierry.reding@gmail.com>
To:     Nicolin Chen <nicoleotsuka@gmail.com>
Cc:     krzk@kernel.org, Joerg Roedel <joro@8bytes.org>,
        linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
        jonathanh@nvidia.com
Subject: Re: [PATCH] memory: tegra: Correct num_tlb_lines for tegra210
Message-ID: <20200917104315.GI3515672@ulmo>
References: <20200915232803.26163-1-nicoleotsuka@gmail.com>
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On Tue, Sep 15, 2020 at 04:28:03PM -0700, Nicolin Chen wrote:
> According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES
> field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines
> should be 48 (0x30) rather than 32 (0x20).
>=20
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
>  drivers/memory/tegra/tegra210.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Please send this as part of a series including:

    https://patchwork.ozlabs.org/project/linux-tegra/patch/20200916002359.1=
0823-1-nicoleotsuka@gmail.com/

Adding Joerg for visibility. From the Tegra side:

Acked-by: Thierry Reding <treding@nvidia.com>

> diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra=
210.c
> index 51b537cfa5a7..4fbf8cbc6666 100644
> --- a/drivers/memory/tegra/tegra210.c
> +++ b/drivers/memory/tegra/tegra210.c
> @@ -1074,7 +1074,7 @@ static const struct tegra_smmu_soc tegra210_smmu_so=
c =3D {
>  	.num_groups =3D ARRAY_SIZE(tegra210_groups),
>  	.supports_round_robin_arbitration =3D true,
>  	.supports_request_limit =3D true,
> -	.num_tlb_lines =3D 32,
> +	.num_tlb_lines =3D 48,
>  	.num_asids =3D 128,
>  };
> =20
> --=20
> 2.17.1
>=20

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