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From:   Krzysztof Kozlowski <krzk@kernel.org>
Date:   Thu, 17 Sep 2020 12:54:42 +0200
Message-ID: <CAJKOXPf5zqJYvaZc102PnTOXKrNYm8fReeJQGGx8eaQDCXavkw@mail.gmail.com>
Subject: Re: [PATCH] memory: tegra: Correct num_tlb_lines for tegra210
To:     Thierry Reding <thierry.reding@gmail.com>
Cc:     Nicolin Chen <nicoleotsuka@gmail.com>,
        Joerg Roedel <joro@8bytes.org>, linux-tegra@vger.kernel.org,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        jonathanh@nvidia.com
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On Thu, 17 Sep 2020 at 12:43, Thierry Reding <thierry.reding@gmail.com> wrote:
>
> On Tue, Sep 15, 2020 at 04:28:03PM -0700, Nicolin Chen wrote:
> > According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES
> > field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines
> > should be 48 (0x30) rather than 32 (0x20).
> >
> > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > ---
> >  drivers/memory/tegra/tegra210.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Please send this as part of a series including:
>
>     https://patchwork.ozlabs.org/project/linux-tegra/patch/20200916002359.10823-1-nicoleotsuka@gmail.com/
>
> Adding Joerg for visibility. From the Tegra side:
>
> Acked-by: Thierry Reding <treding@nvidia.com>

So basically applying this one alone breaks existing platforms and
makes history non-bisectable...

Nicolin, the bisectability is important requirement so you must always
mention the dependencies between patches.

Best regards,
Krzysztof