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[153.199.2.183]) by smtp.googlemail.com with ESMTPSA id 131sm2857634pfy.5.2020.09.18.03.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2020 03:50:03 -0700 (PDT) From: Daniel Palmer To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, mark-pk.tsai@mediatek.com, arnd@arndb.de, maz@kernel.org, linux-kernel@vger.kernel.org, Daniel Palmer Subject: [PATCH 3/3] ARM: mstar: Add interrupt to pm_uart Date: Fri, 18 Sep 2020 19:49:49 +0900 Message-Id: <20200918104949.3260823-4-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200918104949.3260823-1-daniel@0x0f.com> References: <20200918104949.3260823-1-daniel@0x0f.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since we now have support for the interrupt controller pm_uart's interrupt is routed through it make sense to wire up it's interrupt in the device tree. The interrupt is the same for all known chips so it goes in the base dtsi. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index aec841b52ca4..f07880561e11 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -113,6 +113,7 @@ pm_uart: uart@221000 { compatible = "ns16550a"; reg = <0x221000 0x100>; reg-shift = <3>; + interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <172000000>; status = "disabled"; }; -- 2.27.0