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[209.85.217.53]) by smtp.gmail.com with ESMTPSA id 6sm481037vkt.16.2020.09.18.06.59.07 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Sep 2020 06:59:07 -0700 (PDT) Received: by mail-vs1-f53.google.com with SMTP id q13so3604597vsj.13 for ; Fri, 18 Sep 2020 06:59:07 -0700 (PDT) X-Received: by 2002:a67:8bc2:: with SMTP id n185mr12030703vsd.49.1600437546889; Fri, 18 Sep 2020 06:59:06 -0700 (PDT) MIME-Version: 1.0 References: <1600435026-1876-1-git-send-email-srivasam@codeaurora.org> In-Reply-To: <1600435026-1876-1-git-send-email-srivasam@codeaurora.org> From: Doug Anderson Date: Fri, 18 Sep 2020 06:58:55 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3] arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver To: Srinivasa Rao Mandadapu Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Rohit kumar , Srinivas Kandagatla , Ajit Pandey , Cheng-Yi Chiang , V Sujith Kumar Reddy Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Fri, Sep 18, 2020 at 6:18 AM Srinivasa Rao Mandadapu wrote: > > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -1742,6 +1742,45 @@ > }; > }; > > + sec_mi2s_active: sec-mi2s-active { > + pinmux { > + pins = "gpio49", "gpio50", "gpio51"; > + function = "mi2s_1"; > + }; > + > + pinconf { > + pins = "gpio49", "gpio50", "gpio51";; There are still two ";" on the above line.