Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Tue, 22 Sep 2020 10:18:05 +0800
From:   Shawn Guo <shawnguo@kernel.org>
To:     Qiang Zhao <qiang.zhao@nxp.com>
Cc:     robh+dt@kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: layerscape: correct watchdog clocks for
 LS1088A
Message-ID: <20200922021801.GU25109@dragon>
References: <20200914075202.43341-1-qiang.zhao@nxp.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20200914075202.43341-1-qiang.zhao@nxp.com>
User-Agent: Mutt/1.9.4 (2018-02-28)
Precedence: bulk

On Mon, Sep 14, 2020 at 03:52:02PM +0800, Qiang Zhao wrote:
> From: Zhao Qiang <qiang.zhao@nxp.com>
> 
> On LS1088A, watchdog clk are divided by 16, correct it in dts.
> 
> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>

It doesn't apply to my imx/dt64 branch.

Shawn

> ---
>  arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> index b0bbe57..2bd0a71 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> @@ -712,56 +712,56 @@
>  		cluster1_core0_watchdog: wdt@c000000 {
>  			compatible = "arm,sp805-wdt", "arm,primecell";
>  			reg = <0x0 0xc000000 0x0 0x1000>;
> -			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> +			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
>  			clock-names = "apb_pclk", "wdog_clk";
>  		};
>  
>  		cluster1_core1_watchdog: wdt@c010000 {
>  			compatible = "arm,sp805-wdt", "arm,primecell";
>  			reg = <0x0 0xc010000 0x0 0x1000>;
> -			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> +			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
>  			clock-names = "apb_pclk", "wdog_clk";
>  		};
>  
>  		cluster1_core2_watchdog: wdt@c020000 {
>  			compatible = "arm,sp805-wdt", "arm,primecell";
>  			reg = <0x0 0xc020000 0x0 0x1000>;
> -			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> +			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
>  			clock-names = "apb_pclk", "wdog_clk";
>  		};
>  
>  		cluster1_core3_watchdog: wdt@c030000 {
>  			compatible = "arm,sp805-wdt", "arm,primecell";
>  			reg = <0x0 0xc030000 0x0 0x1000>;
> -			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> +			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
>  			clock-names = "apb_pclk", "wdog_clk";
>  		};
>  
>  		cluster2_core0_watchdog: wdt@c100000 {
>  			compatible = "arm,sp805-wdt", "arm,primecell";
>  			reg = <0x0 0xc100000 0x0 0x1000>;
> -			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> +			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
>  			clock-names = "apb_pclk", "wdog_clk";
>  		};
>  
>  		cluster2_core1_watchdog: wdt@c110000 {
>  			compatible = "arm,sp805-wdt", "arm,primecell";
>  			reg = <0x0 0xc110000 0x0 0x1000>;
> -			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> +			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
>  			clock-names = "apb_pclk", "wdog_clk";
>  		};
>  
>  		cluster2_core2_watchdog: wdt@c120000 {
>  			compatible = "arm,sp805-wdt", "arm,primecell";
>  			reg = <0x0 0xc120000 0x0 0x1000>;
> -			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> +			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
>  			clock-names = "apb_pclk", "wdog_clk";
>  		};
>  
>  		cluster2_core3_watchdog: wdt@c130000 {
>  			compatible = "arm,sp805-wdt", "arm,primecell";
>  			reg = <0x0 0xc130000 0x0 0x1000>;
> -			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> +			clocks = <&clockgen 4 15>, <&clockgen 4 15>;
>  			clock-names = "apb_pclk", "wdog_clk";
>  		};
>  
> -- 
> 2.7.4
>