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From:   Rob Herring <robh@kernel.org>
Date:   Wed, 23 Sep 2020 08:13:20 -0600
Message-ID: <CAL_JsqKjzuhLL1UipOVimVb7pt-0KTk3vZ2kX3PssCtRKqhoHw@mail.gmail.com>
Subject: Re: [PATCH] PCI: Cadence: Add quirk for Gen2 controller to do
 autonomous speed change.
To:     Athani Nadeem Ladkhan <nadeem@cadence.com>
Cc:     Tom Joseph <tjoseph@cadence.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        PCI <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Milind Parab <mparab@cadence.com>,
        Swapnil Kashinath Jakhade <sjakhade@cadence.com>
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On Wed, Sep 23, 2020 at 1:54 AM Athani Nadeem Ladkhan
<nadeem@cadence.com> wrote:
>
> Hi Rob,
>
> > -----Original Message-----
> > From: Rob Herring <robh@kernel.org>
> > Sent: Tuesday, September 22, 2020 11:08 PM
> > To: Athani Nadeem Ladkhan <nadeem@cadence.com>
> > Cc: Tom Joseph <tjoseph@cadence.com>; Lorenzo Pieralisi
> > <lorenzo.pieralisi@arm.com>; Bjorn Helgaas <bhelgaas@google.com>; PCI
> > <linux-pci@vger.kernel.org>; linux-kernel@vger.kernel.org; Milind Parab
> > <mparab@cadence.com>; Swapnil Kashinath Jakhade
> > <sjakhade@cadence.com>
> > Subject: Re: [PATCH] PCI: Cadence: Add quirk for Gen2 controller to do
> > autonomous speed change.
> >
> > EXTERNAL MAIL
> >
> >
> > On Fri, Sep 18, 2020 at 4:34 AM Nadeem Athani <nadeem@cadence.com>
> > wrote:
> > >
> > > Cadence controller will not initiate autonomous speed change if
> > > strapped as Gen2. The Retrain bit is set as a quirk to trigger this
> > > speed change.
> > >
> > > Signed-off-by: Nadeem Athani <nadeem@cadence.com>
> > > ---
> > >  drivers/pci/controller/cadence/pcie-cadence-host.c |   13 +++++++++++++
> > >  drivers/pci/controller/cadence/pcie-cadence.h      |    6 ++++++
> > >  2 files changed, 19 insertions(+), 0 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > > b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > > index 4550e0d..4cb7f29 100644
> > > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > > @@ -83,6 +83,8 @@ static int cdns_pcie_host_init_root_port(struct
> > cdns_pcie_rc *rc)
> > >         struct cdns_pcie *pcie = &rc->pcie;
> > >         u32 value, ctrl;
> > >         u32 id;
> > > +       u32 link_cap = CDNS_PCIE_LINK_CAP_OFFSET;
> > > +       u8 sls, lnk_ctl;
> > >
> > >         /*
> > >          * Set the root complex BAR configuration register:
> > > @@ -111,6 +113,17 @@ static int cdns_pcie_host_init_root_port(struct
> > cdns_pcie_rc *rc)
> > >         if (rc->device_id != 0xffff)
> > >                 cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID,
> > > rc->device_id);
> > >
> > > +       /* Quirk to enable autonomous speed change for GEN2 controller */
> > > +       /* Reading Supported Link Speed value */
> > > +       sls = PCI_EXP_LNKCAP_SLS &
> > > +               cdns_pcie_rp_readb(pcie, link_cap + PCI_EXP_LNKCAP);
> > > +       if (sls == PCI_EXP_LNKCAP_SLS_5_0GB) {
> > > +               /* Since this a Gen2 controller, set Retrain Link(RL) bit */
> > > +               lnk_ctl = cdns_pcie_rp_readb(pcie, link_cap + PCI_EXP_LNKCTL);
> > > +               lnk_ctl |= PCI_EXP_LNKCTL_RL;
> > > +               cdns_pcie_rp_writeb(pcie, link_cap + PCI_EXP_LNKCTL,
> > > + lnk_ctl);
> >
> > Why the byte accesses? This is a 16-bit register.
> This is a 32bit register. But the register field require is at first byte only. Hence the byte access.

No, it's a 16-bit register as Link Status is at the next half word:

#define PCI_EXP_LNKCTL 16 /* Link Control */
#define PCI_EXP_LNKSTA 18 /* Link Status */

Use accesses that match the register size.

Rob