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From:   Sagar Kadam <sagar.kadam@openfive.com>
To:     Rob Herring <robh@kernel.org>
CC:     "linux-pwm@vger.kernel.org" <linux-pwm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
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        "mturquette@baylibre.com" <mturquette@baylibre.com>,
        "sboyd@kernel.org" <sboyd@kernel.org>,
        "Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com>,
        "palmer@dabbelt.com" <palmer@dabbelt.com>,
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        "aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
        Yash Shah <yash.shah@openfive.com>
Subject: RE: [PATCH v1 2/3] dt-bindings: riscv: convert plic bindings to
 json-schema
Thread-Topic: [PATCH v1 2/3] dt-bindings: riscv: convert plic bindings to
 json-schema
Thread-Index: AQHWh19i+MNhYtLbO0WaWaqZxwh8y6l1MMuAgAElMQA=
Date:   Wed, 23 Sep 2020 17:33:35 +0000
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Hello Rob,

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Wednesday, September 23, 2020 2:04 AM
> To: Sagar Kadam <sagar.kadam@openfive.com>
> Cc: linux-pwm@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> riscv@lists.infradead.org; devicetree@vger.kernel.org; linux-
> clk@vger.kernel.org; mturquette@baylibre.com; sboyd@kernel.org; Paul
> Walmsley ( Sifive) <paul.walmsley@sifive.com>; palmer@dabbelt.com;
> tglx@linutronix.de; jason@lakedaemon.net; maz@kernel.org;
> thierry.reding@gmail.com; u.kleine-koenig@pengutronix.de;
> lee.jones@linaro.org; aou@eecs.berkeley.edu; Yash Shah
> <yash.shah@openfive.com>
> Subject: Re: [PATCH v1 2/3] dt-bindings: riscv: convert plic bindings to =
json-
> schema
>=20
> [External Email] Do not click links or attachments unless you recognize t=
he
> sender and know the content is safe
>=20
> On Thu, Sep 10, 2020 at 04:14:03PM +0530, Sagar Kadam wrote:
> > Convert device tree bindings for SiFive's PLIC to YAML format
> >
> > Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>
> > ---
> >  .../interrupt-controller/sifive,plic-1.0.0.txt     |  58 -----------
> >  .../interrupt-controller/sifive,plic-1.0.0.yaml    | 107
> +++++++++++++++++++++
> >  2 files changed, 107 insertions(+), 58 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.txt
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.txt
> b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-
> 1.0.0.txt
> > deleted file mode 100644
> > index 6adf7a6..0000000
> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,pli=
c-
> 1.0.0.txt
> > +++ /dev/null
> > @@ -1,58 +0,0 @@
> > -SiFive Platform-Level Interrupt Controller (PLIC)
> > --------------------------------------------------
> > -
> > -SiFive SOCs include an implementation of the Platform-Level Interrupt
> Controller
> > -(PLIC) high-level specification in the RISC-V Privileged Architecture
> > -specification.  The PLIC connects all external interrupts in the syste=
m to all
> > -hart contexts in the system, via the external interrupt source in each=
 hart.
> > -
> > -A hart context is a privilege mode in a hardware execution thread.  Fo=
r
> example,
> > -in an 4 core system with 2-way SMT, you have 8 harts and probably at
> least two
> > -privilege modes per hart; machine mode and supervisor mode.
> > -
> > -Each interrupt can be enabled on per-context basis.  Any context can c=
laim
> > -a pending enabled interrupt and then release it once it has been handl=
ed.
> > -
> > -Each interrupt has a configurable priority.  Higher priority interrupt=
s are
> > -serviced first.  Each context can specify a priority threshold. Interr=
upts
> > -with priority below this threshold will not cause the PLIC to raise it=
s
> > -interrupt line leading to the context.
> > -
> > -While the PLIC supports both edge-triggered and level-triggered interr=
upts,
> > -interrupt handlers are oblivious to this distinction and therefore it =
is not
> > -specified in the PLIC device-tree binding.
> > -
> > -While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
> > -"sifive,plic-1.0.0" device is a concrete implementation of the PLIC th=
at
> > -contains a specific memory layout, which is documented in chapter 8 of
> the
> > -SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC=
-
> RVCoreIP.pdf>.
> > -
> > -Required properties:
> > -- compatible : "sifive,plic-1.0.0" and a string identifying the actual
> > -  detailed implementation in case that specific bugs need to be worked
> around.
> > -- #address-cells : should be <0> or more.
> > -- #interrupt-cells : should be <1> or more.
> > -- interrupt-controller : Identifies the node as an interrupt controlle=
r.
> > -- reg : Should contain 1 register range (address and length).
> > -- interrupts-extended : Specifies which contexts are connected to the =
PLIC,
> > -  with "-1" specifying that a context is not present.  Each node point=
ed
> > -  to should be a riscv,cpu-intc node, which has a riscv node as parent=
.
> > -- riscv,ndev: Specifies how many external interrupts are supported by
> > -  this controller.
> > -
> > -Example:
> > -
> > -     plic: interrupt-controller@c000000 {
> > -             #address-cells =3D <0>;
> > -             #interrupt-cells =3D <1>;
> > -             compatible =3D "sifive,plic-1.0.0", "sifive,fu540-c000-pl=
ic";
> > -             interrupt-controller;
> > -             interrupts-extended =3D <
> > -                     &cpu0-intc 11
> > -                     &cpu1-intc 11 &cpu1-intc 9
> > -                     &cpu2-intc 11 &cpu2-intc 9
> > -                     &cpu3-intc 11 &cpu3-intc 9
> > -                     &cpu4-intc 11 &cpu4-intc 9>;
> > -             reg =3D <0xc000000 0x4000000>;
> > -             riscv,ndev =3D <10>;
> > -     };
> > diff --git a/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-
> 1.0.0.yaml
> > new file mode 100644
> > index 0000000..95c8c85
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,pli=
c-
> 1.0.0.yaml
> > @@ -0,0 +1,107 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +# Copyright (C) 2020 SiFive, Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-
> 1.0.0.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SiFive Platform-Level Interrupt Controller (PLIC)
> > +
> > +description:
> > +  SiFive SOCs include an implementation of the Platform-Level Interrup=
t
> Controller
> > +  (PLIC) high-level specification in the RISC-V Privileged Architectur=
e
> > +  specification. The PLIC connects all external interrupts in the syst=
em to all
> > +  hart contexts in the system, via the external interrupt source in ea=
ch
> hart.
> > +
> > +  A hart context is a privilege mode in a hardware execution thread. F=
or
> example,
> > +  in an 4 core system with 2-way SMT, you have 8 harts and probably at
> least two
> > +  privilege modes per hart; machine mode and supervisor mode.
> > +
> > +  Each interrupt can be enabled on per-context basis. Any context can
> claim
> > +  a pending enabled interrupt and then release it once it has been
> handled.
> > +
> > +  Each interrupt has a configurable priority. Higher priority interrup=
ts are
> > +  serviced first.  Each context can specify a priority threshold. Inte=
rrupts
> > +  with priority below this threshold will not cause the PLIC to raise =
its
> > +  interrupt line leading to the context.
> > +
> > +  While the PLIC supports both edge-triggered and level-triggered
> interrupts,
> > +  interrupt handlers are oblivious to this distinction and therefore i=
t is not
> > +  specified in the PLIC device-tree binding.
> > +
> > +  While the RISC-V ISA doesn't specify a memory layout for the PLIC, t=
he
> > +  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC =
that
> > +  contains a specific memory layout, which is documented in chapter 8 =
of
> the
> > +  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-=
MC-
> RVCoreIP.pdf>.
> > +
> > +maintainers:
> > +  - Sagar Kadam <sagar.kadam@sifive.com>
> > +  - Paul Walmsley  <paul.walmsley@sifive.com>
> > +  - Palmer Dabbelt <palmer@dabbelt.com>
> > +
> > +allOf:
> > +  - $ref: /schemas/interrupt-controller.yaml#
>=20
> Don't need this. It gets selected matching on node name.
>=20
Thanks for your suggestions. I will incorporate your suggestions and send t=
he v2.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: sifive,plic-1.0.0
> > +      - const: sifive,fu540-c000-plic
>=20
> Somehow these ended up in the wrong order. Should be most specific to
> least specific.
>=20
Yes, will rectify this.
> > +
> > +    description:
> > +      Should be "sifive,plic-1.0.0" and a string identifying the actua=
l
> > +      detailed implementation in case that specific bugs need to be wo=
rked
> around.
>=20
> Drop this.
>=20
> > +
> > +  reg:
> > +    maxItems: 1
> > +    description:  Should contain 1 register range (address and length)=
.
>=20
> Drop this. The schema says this...
>=20
> > +
> > +  '#address-cells':
> > +    const: 0
> > +    description: Should be <0> or more.
>=20
> Drop. 'or more' is wrong. If there's a case with more, it will need to
> be documented.
>=20
> > +
> > +  '#interrupt-cells':
> > +    const: 1
> > +    description: Should be <1> or more.
>=20
> Same here.
>=20
Okay.=20
Will remove as suggested above

Thanks & BR,
Sagar

> > +
> > +  interrupt-controller: true
> > +
> > +  interrupts-extended:
> > +    minItems: 1
> > +    description:
> > +      Specifies which contexts are connected to the PLIC, with "-1" sp=
ecifying
> > +      that a context is not present. Each node pointed to should be a
> > +      riscv,cpu-intc node, which has a riscv node as parent.
> > +
> > +  riscv,ndev:
> > +    $ref: "/schemas/types.yaml#/definitions/uint32"
> > +    description:
> > +      Specifies how many external interrupts are supported by this
> controller.
> > +
> > +required:
> > +  - compatible
> > +  - '#address-cells'
> > +  - '#interrupt-cells'
> > +  - interrupt-controller
> > +  - reg
> > +  - interrupts-extended
> > +  - riscv,ndev
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    plic: interrupt-controller@c000000 {
> > +      #address-cells =3D <0>;
> > +      #interrupt-cells =3D <1>;
> > +      compatible =3D "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
> > +      interrupt-controller;
> > +      interrupts-extended =3D <
> > +        &cpu0_intc 11
> > +        &cpu1_intc 11 &cpu1_intc 9
> > +        &cpu2_intc 11 &cpu2_intc 9
> > +        &cpu3_intc 11 &cpu3_intc 9
> > +        &cpu4_intc 11 &cpu4_intc 9>;
> > +      reg =3D <0xc000000 0x4000000>;
> > +      riscv,ndev =3D <10>;
> > +    };
> > --
> > 2.7.4
> >