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From:   Felipe Balbi <balbi@kernel.org>
To:     Rob Herring <robh@kernel.org>,
        Manish Narani <manish.narani@xilinx.com>
Cc:     gregkh@linuxfoundation.org, michal.simek@xilinx.com,
        p.zabel@pengutronix.de, linux-usb@vger.kernel.org,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, git@xilinx.com
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation
 for Versal DWC3 Controller
In-Reply-To: <20200922195410.GA3122345@bogus>
References: <1599678185-119412-1-git-send-email-manish.narani@xilinx.com>
 <1599678185-119412-2-git-send-email-manish.narani@xilinx.com>
 <20200922195410.GA3122345@bogus>
Date:   Thu, 24 Sep 2020 10:16:41 +0300
Message-ID: <87wo0jejae.fsf@kernel.org>
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Rob Herring <robh@kernel.org> writes:

> On Thu, Sep 10, 2020 at 12:33:04AM +0530, Manish Narani wrote:
>> Add documentation for Versal DWC3 controller. Add required property
>> 'reg' for the same. Also add optional properties for snps,dwc3.
>>=20
>> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
>> ---
>>  .../devicetree/bindings/usb/dwc3-xilinx.txt   | 20 +++++++++++++++++--
>>  1 file changed, 18 insertions(+), 2 deletions(-)
>>=20
>> diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Doc=
umentation/devicetree/bindings/usb/dwc3-xilinx.txt
>> index 4aae5b2cef56..219b5780dbee 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
>> @@ -1,7 +1,8 @@
>>  Xilinx SuperSpeed DWC3 USB SoC controller
>>=20=20
>>  Required properties:
>> -- compatible:	Should contain "xlnx,zynqmp-dwc3"
>> +- compatible:	May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
>> +- reg:		Base address and length of the register control block
>>  - clocks:	A list of phandles for the clocks listed in clock-names
>>  - clock-names:	Should contain the following:
>>    "bus_clk"	 Master/Core clock, have to be >=3D 125 MHz for SS
>> @@ -13,12 +14,24 @@ Required child node:
>>  A child node must exist to represent the core DWC3 IP block. The name of
>>  the node is not important. The content of the node is defined in dwc3.t=
xt.
>>=20=20
>> +Optional properties for snps,dwc3:
>> +- dma-coherent:	Enable this flag if CCI is enabled in design. Adding th=
is
>> +		flag configures Global SoC bus Configuration Register and
>> +		Xilinx USB 3.0 IP - USB coherency register to enable CCI.
>> +- snps,enable-hibernation: Add this flag to enable hibernation support =
for
>> +		peripheral mode.
>
> This belongs in the DWC3 binding. It also implies that hibernation is=20
> not supported by any other DWC3 based platform. Can't this be implied by=
=20
> the compatible string (in the parent)?

hibernation support is detectable in runtime, and we've been using that.

=2D-=20
balbi

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