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Date:   Thu, 24 Sep 2020 12:23:12 +0200
From:   Thierry Reding <thierry.reding@gmail.com>
To:     Nicolin Chen <nicoleotsuka@gmail.com>
Cc:     joro@8bytes.org, linux-kernel@vger.kernel.org,
        iommu@lists.linux-foundation.org, linux-tegra@vger.kernel.org,
        jonathanh@nvidia.com, vdumpa@nvidia.com
Subject: Re: [PATCH 1/3] iommu/tegra-smmu: Do not use PAGE_SHIFT and PAGE_MASK
Message-ID: <20200924102312.GG2483160@ulmo>
References: <20200911071643.17212-1-nicoleotsuka@gmail.com>
 <20200911071643.17212-2-nicoleotsuka@gmail.com>
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On Fri, Sep 11, 2020 at 12:16:41AM -0700, Nicolin Chen wrote:
> PAGE_SHIFT and PAGE_MASK are defined corresponding to the page size
> for CPU virtual addresses, which means PAGE_SHIFT could be a number
> other than 12, but tegra-smmu maintains fixed 4KB IOVA pages and has
> fixed [21:12] bit range for PTE entries.
>=20
> So this patch replaces all PAGE_SHIFT/PAGE_MASK references with the
> macros defined with SMMU_PTE_SHIFT.
>=20
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
>  drivers/iommu/tegra-smmu.c | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
>=20
> diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
> index 046add7acb61..789d21c01b77 100644
> --- a/drivers/iommu/tegra-smmu.c
> +++ b/drivers/iommu/tegra-smmu.c
> @@ -130,6 +130,11 @@ static inline u32 smmu_readl(struct tegra_smmu *smmu=
, unsigned long offset)
>  #define SMMU_PDE_SHIFT 22
>  #define SMMU_PTE_SHIFT 12
> =20
> +#define SMMU_PAGE_MASK		(~(SMMU_SIZE_PT-1))
> +#define SMMU_OFFSET_IN_PAGE(x)	((unsigned long)(x) & ~SMMU_PAGE_MASK)
> +#define SMMU_PFN_PHYS(x)	((phys_addr_t)(x) << SMMU_PTE_SHIFT)
> +#define SMMU_PHYS_PFN(x)	((unsigned long)((x) >> SMMU_PTE_SHIFT))
> +
>  #define SMMU_PD_READABLE	(1 << 31)
>  #define SMMU_PD_WRITABLE	(1 << 30)
>  #define SMMU_PD_NONSECURE	(1 << 29)
> @@ -644,7 +649,7 @@ static void tegra_smmu_set_pte(struct tegra_smmu_as *=
as, unsigned long iova,
>  			       u32 *pte, dma_addr_t pte_dma, u32 val)
>  {
>  	struct tegra_smmu *smmu =3D as->smmu;
> -	unsigned long offset =3D offset_in_page(pte);
> +	unsigned long offset =3D SMMU_OFFSET_IN_PAGE(pte);
> =20
>  	*pte =3D val;
> =20
> @@ -726,7 +731,7 @@ __tegra_smmu_map(struct iommu_domain *domain, unsigne=
d long iova,
>  		pte_attrs |=3D SMMU_PTE_WRITABLE;
> =20
>  	tegra_smmu_set_pte(as, iova, pte, pte_dma,
> -			   __phys_to_pfn(paddr) | pte_attrs);
> +			   SMMU_PHYS_PFN(paddr) | pte_attrs);
> =20
>  	return 0;
>  }
> @@ -790,7 +795,7 @@ static phys_addr_t tegra_smmu_iova_to_phys(struct iom=
mu_domain *domain,
> =20
>  	pfn =3D *pte & as->smmu->pfn_mask;
> =20
> -	return PFN_PHYS(pfn);
> +	return SMMU_PFN_PHYS(pfn);
>  }
> =20
>  static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
> @@ -1108,7 +1113,8 @@ struct tegra_smmu *tegra_smmu_probe(struct device *=
dev,
>  	smmu->dev =3D dev;
>  	smmu->mc =3D mc;
> =20
> -	smmu->pfn_mask =3D BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1;
> +	smmu->pfn_mask =3D
> +		BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1;

checkpatch no longer warns about lines longer than 80 characters. The
new limit is 100, so you can fit this all on one line.

But either way:

Acked-by: Thierry Reding <treding@nvidia.com>

--/i8j2F0k9BYX4qLc
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl9sc5AACgkQ3SOs138+
s6F80g/+JuxY/x6E7mY8d3iXr0sk56VhC9IAKa2ZyE5iUaD2Con2ohzLEZQ9zOCS
GSQqZuiQiP+9l6k296/0wKd2NV9Y9g86JBmyEghk0YBCpqqoR8eklPmpL4D/vXwx
CjwqxnQ8Qm0nAUTkOLYC1bygUJ6eELDD/P8z2pU/Gex6hLTFP93PbRkpnjke8poS
beDTJGgBpQFSJ3vv3+R/nTAbWtI1ErWIugpSxiRUrBr8E7H8M9dyYVknKk49Ejjo
3+PUYW7GmuUnvtbs5fI9oPZ5ydgeL92QK38OLgVzAOnnULvcrwLCXrxATIrPJ9sD
qURSWQa2mOE+NFQ7z7+Z0qDt48FjQoGj6IGFjQur+wWulZiSLRiZP5s3u+k6aOU8
oPl1uMwDf2UEQLT8CGNR02z/0VBCV/WwFx1fXAaTqu5wBsdVAzIKe5dCQDk+c74O
KwXzkzvNvsfGSJ2DlMi/iJC0CETD2UlBfGZnCDOv5fzWYkXotHn9smqKNv0ihbMO
s9dCY0lYd8PhjLL//qY18WPXmM5s3HjxPUJmU/wmKUIYofJR6+xmmksqtWBydjiv
l5R0TopIsLDRQ739sGdW3yUvgbYHdXq51oExrkZSh+BKJoobwazDgBP4CR7UVpXO
Uxl+wVcC7qo4g2AFCb9iMmrw7o6hvpW+G3JpT5vcMCqCX5/DjZc=
=JXY2
-----END PGP SIGNATURE-----

--/i8j2F0k9BYX4qLc--