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Date:   Fri, 25 Sep 2020 09:22:31 +0200
From:   Borislav Petkov <bp@alien8.de>
To:     Yazen Ghannam <yazen.ghannam@amd.com>
Cc:     linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
        tony.luck@intel.com, x86@kernel.org,
        Smita.KoralahalliChannabasappa@amd.com
Subject: Re: [PATCH v2 8/8] x86/MCE/AMD Support new memory interleaving modes
 during address translation
Message-ID: <20200925072231.GC16872@zn.tnic>
References: <20200903200144.310991-1-Yazen.Ghannam@amd.com>
 <20200903200144.310991-9-Yazen.Ghannam@amd.com>
 <20200923082039.GB28545@zn.tnic>
 <20200923162510.GB1684790@yaz-nikka.amd.com>
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On Wed, Sep 23, 2020 at 11:25:10AM -0500, Yazen Ghannam wrote:
> I don't remember the original reason, and I was recently asked about
> this code living in a module. I did some looking after this ask, and I
> found that we should be using this translation to get a proper value for
> the memory error notifiers to use. So I think we still need to use this
> function some way with the core code even if the EDAC interface isn't
> used.

You'd need to be more specific here, you want to bypass amd64_edac to
decode errors? Judging by the current RAS activity coming from you guys,
I'm thinking firmware. But then wouldn't the firmware do the decoding
for us and then this function is not even needed?

> What do you think?

I think you should explain what the use case is first. :)

Thx.

-- 
Regards/Gruss,
    Boris.

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