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Fri, 25 Sep 2020 09:59:14 +0000 Subject: Re: [PATCH 02/13] iommu: amd: Prepare for generic IO page table framework To: Robin Murphy , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org References: <20200923101442.73157-1-suravee.suthikulpanit@amd.com> <20200923101442.73157-3-suravee.suthikulpanit@amd.com> From: Suravee Suthikulpanit Message-ID: Date: Fri, 25 Sep 2020 16:58:53 +0700 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Originating-IP: [165.204.80.7] X-ClientProxiedBy: KL1PR01CA0127.apcprd01.prod.exchangelabs.com (2603:1096:820:4::19) To DM5PR12MB1163.namprd12.prod.outlook.com (2603:10b6:3:7a::18) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from Suravees-MacBook-Pro.local (165.204.80.7) by KL1PR01CA0127.apcprd01.prod.exchangelabs.com (2603:1096:820:4::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3412.20 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: weNmVd7+tgoO/3e15SRcTVSCmy2OtQw8j81L6dIhYheHMSnsxOkaBnKar/0VGWrKHRBxjgsF45tvM3OGcMmSq+fFZzg0ZpZYWpO2lgwPDNvAIo2PmS4OKV9d1jkJAeXsCWkMKUbpeVLLgTrLR3KnQa61y6CcfXIYto8AsweDXHK8kuQS/7dIx5RoTTKyiWVCSy43BblBfyH78fDq+H+d4cm8jmFZKBH2gpQ/nkksfBBC9vRpGkpv2Srf3nrk3okcUStxlVbkmu8AdhpLqnhVKIs2A/c609/1cNWcWSOlwF5BBlHZLK5VTnMnvDZ1/Xv2qW17eyMu3E0SSd4QO0MvqkdMfA3j2hyMFs1F0W7nOi6pEdP2WNJS6sySwG3O7JYpFOLLwB15N7P2V7/tHNvOzrQLThDfrFVbUt+jB526hUh8Az4zxQmsyxn9wKPWmy2fAj+HfRr+dRv8SvXVFi11EQ+FBpTu/AV6QMOg8vHyAdf7OgkqaMhg2iYkdKhzReiJ/G2h1rwBntq1PHtEZhJYMMwHpqvaa1AgdFIhMHkVH7lw4FuK9sNgbwxpfSu1Bg62wYCsTtXz4XUBZJzRbfreRfdgtMoQ32fw9BEORcaBT2HGeKxceW+oUzGUsumIoopr3jNd+eBJrFHCj3DhbOOv3g== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b292f264-6e62-4dc9-b4cc-08d86139a88e X-MS-Exchange-CrossTenant-AuthSource: DM5PR12MB1163.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2020 09:59:14.3479 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: h2zJFh3YN7EeBMEBE31dfwKGyo9GCwoFvkhXFMm29CE4UveqzQPFCni3qSvCoVqJNBmRC6Ly3bnlAL1+5arpHQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0220 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Robin, On 9/24/20 7:25 PM, Robin Murphy wrote: >> +struct io_pgtable_ops *amd_iommu_setup_io_pgtable_ops(struct iommu_dev_data *dev_data, >> +                         struct protection_domain *domain) >> +{ >> +        domain->iop.pgtbl_cfg = (struct io_pgtable_cfg) { >> +        .pgsize_bitmap    = AMD_IOMMU_PGSIZES, >> +        .ias        = IOMMU_IN_ADDR_BIT_SIZE, >> +        .oas        = IOMMU_OUT_ADDR_BIT_SIZE, >> +        .coherent_walk    = false, > > Is that right? Given that you seem to use regular kernel addresses for pagetable pages and don't have any obvious cache > maintenance around PTE manipulation, I suspect not ;) > > It's fair enough if your implementation doesn't use this and simply assumes coherency, but in that case it would be less > confusing to have the driver set it to true for the sake of honesty, or just leave it out > entirely - explicitly setting false gives the illusion of being meaningful. AMD IOMMU can be configured to disable snoop for page table walk of a particular device (DTE[SD]=1). However, the current Linux driver does not set this bit, which should assume coherency. We can just leaving this out for now. I can remove this when I send out V2 along w/ other changes. > Otherwise, the io-pgtable parts all look OK to me - it's nice to finally > fulfil the original intent of not being an Arm-specific thing :D > > Robin. Thanks, Suravee