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Message-ID: <9e6560a23a6b02fd9c041983bf2d843de1f7618e.camel@pengutronix.de>
From:   Lucas Stach <l.stach@pengutronix.de>
To:     Christian Gmeiner <christian.gmeiner@gmail.com>,
        linux-kernel@vger.kernel.org
Cc:     David Airlie <airlied@linux.ie>, etnaviv@lists.freedesktop.org,
        dri-devel@lists.freedesktop.org, Daniel Vetter <daniel@ffwll.ch>,
        Russell King <linux+etnaviv@armlinux.org.uk>, cphealy@gmail.com
Date:   Fri, 25 Sep 2020 12:08:27 +0200
In-Reply-To: <20200814090512.151416-4-christian.gmeiner@gmail.com>
References: <20200814090512.151416-1-christian.gmeiner@gmail.com>
         <20200814090512.151416-4-christian.gmeiner@gmail.com>
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Subject: Re: [PATCH 3/4] drm/etnaviv: add total hi bandwidth perfcounter
Precedence: bulk

On Fr, 2020-08-14 at 11:05 +0200, Christian Gmeiner wrote:
> These two perf counters represent the total read and write
> GPU bandwidth in terms of 64bits.
> 
> The used sequence was taken from Vivante kernel driver.
> 
> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> ---
>  drivers/gpu/drm/etnaviv/etnaviv_perfmon.c | 35 ++++++++++++++++++++++-
>  1 file changed, 34 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> index 782732e6ce72..b37459f022d7 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> @@ -69,6 +69,29 @@ static u32 pipe_perf_reg_read(struct etnaviv_gpu *gpu,
>  	return value;
>  }
>  
> +static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
> +	const struct etnaviv_pm_domain *domain,
> +	const struct etnaviv_pm_signal *signal)
> +{
> +	u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
> +	u32 value = 0;
> +	unsigned i;
> +
> +	for (i = 0; i < gpu->identity.pixel_pipes; i++) {
> +		clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
> +		clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(i);
> +		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
> +		value += gpu_read(gpu, signal->data);
> +	}
> +
> +	/* switch back to pixel pipe 0 to prevent GPU hang */
> +	clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
> +	clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(0);
> +	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
> +
> +	return value;
> +}
> +
>  static u32 hi_total_cycle_read(struct etnaviv_gpu *gpu,
>  	const struct etnaviv_pm_domain *domain,
>  	const struct etnaviv_pm_signal *signal)
> @@ -102,8 +125,18 @@ static const struct etnaviv_pm_domain doms_3d[] = {
>  		.name = "HI",
>  		.profile_read = VIVS_MC_PROFILE_HI_READ,
>  		.profile_config = VIVS_MC_PROFILE_CONFIG2,
> -		.nr_signals = 5,
> +		.nr_signals = 7,

I've tripped across this part. It's something I don't particularly
like, as this value has a risk of getting inconsistent with the actual
array. Maybe we could split out signal array from this initialization,
so we could then use the ARRAY_SIZE macro to initialize this value?

But that's not really related to this patch and can be done in a
follow-up cleanup.

Regards,
Lucas

>  		.signal = (const struct etnaviv_pm_signal[]) {
> +			{
> +				"TOTAL_READ_BYTES8",
> +				VIVS_HI_PROFILE_READ_BYTES8,
> +				&pipe_reg_read,
> +			},
> +			{
> +				"TOTAL_WRITE_BYTES8",
> +				VIVS_HI_PROFILE_WRITE_BYTES8,
> +				&pipe_reg_read,
> +			},
>  			{
>  				"TOTAL_CYCLES",
>  				0,