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Date:   Sat, 26 Sep 2020 01:03:29 +0300
From:   Vladimir Oltean <olteanv@gmail.com>
To:     Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
        f.fainelli@gmail.com
Cc:     netdev@vger.kernel.org, linux-amlogic@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux@armlinux.org.uk, peppe.cavallaro@st.com,
        alexandre.torgue@st.com, joabreu@synopsys.com, davem@davemloft.net,
        kuba@kernel.org
Subject: Re: RGMII timing calibration (on 12nm Amlogic SoCs) - integration
 into dwmac-meson8b
Message-ID: <20200925220329.wdnrqeauto55vdao@skbuf>
References: <CAFBinCATt4Hi9rigj52nMf3oygyFbnopZcsakGL=KyWnsjY3JA@mail.gmail.com>
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Hi Martin,

On Fri, Sep 25, 2020 at 11:47:18PM +0200, Martin Blumenstingl wrote:
> Hello,
>
> Amlogic's 12nm SoC generation requires some RGMII timing calibration
> within the Ethernet controller glue registers.
> This calibration is only needed for the RGMII modes, not for the
> (internal) RMII PHY.
> With "incorrect" calibration settings Ethernet speeds up to 100Mbit/s
> will still work fine, but no data is flowing on 1Gbit/s connections
> (similar to when RX or TX delay settings are incorrect).
>
> A high-level description of this calibration (the full code can be
> seen in [0] and [1]):
> - there are sixteen possible calibration values: [0..15]
> - switch the Ethernet PHY to loopback mode
> - for each of the sixteen possible calibration values repeat the
> following steps five times:
> -- write the value to the calibration register
> -- construct an Ethernet loopback test frame with protocol 0x0808
> ("Frame Relay ARP")
> -- add 256 bytes of arbitrary data
> -- use the MAC address of the controller as source and destination
> -- send out this data packet
> -- receive this data packet
> -- compare the contents and remember if the data is valid or corrupted
> - disable loopback mode on the Ethernet PHY
> - find the best calibration value by getting the center point of the
> "longest streak"
> - write this value to the calibration register
>
> My question is: how do I integrate this into the dwmac-meson8b (stmmac
> based) driver?
> I already found some interesting and relevant bits:
> - stmmac_selftests.c uses phy_loopback() and also constructs data
> which is sent-out in loopback mode
> - there's a serdes_powerup callback in struct plat_stmmacenet_data
> which is called after register_netdev()
> - I'm not sure if there's any other Ethernet driver doing some similar
> calibration (and therefore a way to avoid some code-duplication)
>
>
> Any recommendations/suggestions/ideas/hints are welcome!
> Thank you and best regards,
> Martin
>
>
> [0] https://github.com/khadas/u-boot/blob/4752efbb90b7d048a81760c67f8c826f14baf41c/drivers/net/designware.c#L707
> [1] https://github.com/khadas/linux/blob/khadas-vims-4.9.y/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c#L466

Florian attempted something like this before, for the PHY side of things:
https://patchwork.ozlabs.org/project/netdev/patch/20191015224953.24199-3-f.fainelli@gmail.com/

There are quite some assumptions to be made if the code is to be made
generic, such as the fact that the controller should not drop frames
with bad FCS in hardware. Or if it does, the code should be aware of
that and check that counter.

Thanks,
-Vladimir