Received: by 2002:a05:6a10:22f:0:0:0:0 with SMTP id 15csp1866697pxk; Sat, 26 Sep 2020 07:47:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxuxecG81PGxnBLLmoURtOdnOVyYM4CVnAEbvx6zBSpd/k60RGBZMaPfH+QPfn9KpfE2x9t X-Received: by 2002:aa7:d1ce:: with SMTP id g14mr7010952edp.153.1601131644496; Sat, 26 Sep 2020 07:47:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601131644; cv=none; d=google.com; s=arc-20160816; b=HVQU/DpX40nUlS640MSUkIhxefBQw/C4mp0u8k81ajVKys7RuMDW/RI+IPBFkdorX3 R++ZD65std4KgwKe8KZaP5asAzmiQUbk0+kI9mWE0npmIajDUOYTEaMI/zHZzC4594xE 39BUEqBxtK9YisnvgUx564lCBTtxem9O6r/p+L+Y9CFPBY3PMv5kGdWxdyazjh/wXQ0K tFcLoheCfRnExgYKDKAghsEZm7iwGRLoLuohaOIX5V68M7fwPqJcHhgZmp9nEZ5FmE4E E0jRBpUEgEmcVkeE7sswt/qs/VxyLiXgSTGh5gl7dQPs9kjWr3pTNpCfodoeaYbgMS3Z k4Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=/CajTmdws2mRjvaYsBA3l+2UlpYRO0cOypMqZgPeuqE=; b=PduHRCToU85JyD1N5IOqFX8w3o9yhHrQ3Dyf4wBIt16B77G9ZcE1blBsvHpetgi9nt wBokd7k6QnpMDwTkyvIpJ3NZbXzdBP24gAIKloQMgwEZRFoMogGSgexzwtIbhaPxXXmj BN4fHbhZ1AufhY8OPs6Mzi8UysP1NRNm8MKZ+D+yRk6sHJXQRaWfwNKN3P/L4Gg8iYYH BPcRMH/RObH/RDhcHWnFMDKS/41O23jR6nNjiWJq3TNqb2rZo003Mm2gxy0YhUMMo/Wj MI0NQqm9W0QlKhqOAbKtaPdf60JM76J+GU7YwXkF+fG5IwWfM5ah51HfBX1BWba2VCTe ex7A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r27si4012859edw.410.2020.09.26.07.47.01; Sat, 26 Sep 2020 07:47:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729478AbgIZOpT (ORCPT + 99 others); Sat, 26 Sep 2020 10:45:19 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:56714 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729356AbgIZOpS (ORCPT ); Sat, 26 Sep 2020 10:45:18 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kMBRp-00GHdg-P1; Sat, 26 Sep 2020 16:45:13 +0200 Date: Sat, 26 Sep 2020 16:45:13 +0200 From: Andrew Lunn To: Martin Blumenstingl Cc: netdev@vger.kernel.org, linux-amlogic@lists.infradead.org, alexandre.torgue@st.com, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, joabreu@synopsys.com, kuba@kernel.org, peppe.cavallaro@st.com, davem@davemloft.net, linux-arm-kernel@lists.infradead.org Subject: Re: RGMII timing calibration (on 12nm Amlogic SoCs) - integration into dwmac-meson8b Message-ID: <20200926144513.GD3850848@lunn.ch> References: <20200925221403.GE3856392@lunn.ch> <20200926004129.GC3850848@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > I checked this again for the vendor u-boot (where Ethernet is NOT > working) as well as the Android kernel which this board was shipped > with (where Ethernet is working) > - in u-boot the MAC side adds a 2ns TX delay and the PHY side adds a > 2ns RX delay So that suggest there is nothing on the PCB. It is all down to MAC and PHY adding delays. > yes, there's only one calibration value > the reference code is calculating the calibration setting for four > configuration variants: > - 2ns TX delay on the MAC side, no RX or TX delay on the PHY side, RGMII RX_CLK not inverted > - 2ns TX delay on the MAC side, no RX or TX delay on the PHY side, RGMII RX_CLK inverted > - 2ns TX delay on the MAC side, 2ns RX delay on the PHY side, RGMII RX_CLK not inverted > - 2ns TX delay on the MAC side, 2ns RX delay on the PHY side, RGMII RX_CLK inverted > > now that I'm writing this, could it be a calibration of the RX_CLK > signal? Yes, seems like it. Which of these four does it end up using? I'm guessing the 3rd? So i would forget about configuration clock inversion. Hard code it to whatever works. It is not something you see other MAC/PHY combinations allow to configure. I think you said a value of 0x2 works. I wonder if that corresponds to something slightly larger than 0ns if option 3 is being used? > In the meantime Amlogic's "hacked" PHY driver is also using these registers: [0] > So I assume that I'm doing the right thing in the Realtek PHY driver Thanks for confirming this. No need to check for the resistors. Andrew