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[23.128.96.18]) by mx.google.com with ESMTP id b19si7030070edy.519.2020.09.27.23.21.18; Sun, 27 Sep 2020 23:21:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@jms.id.au header.s=google header.b=LGn8ICS8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726558AbgI1GRi (ORCPT + 99 others); Mon, 28 Sep 2020 02:17:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726412AbgI1GRi (ORCPT ); Mon, 28 Sep 2020 02:17:38 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94050C0613CE; Sun, 27 Sep 2020 23:17:37 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id p15so6830868ejm.7; Sun, 27 Sep 2020 23:17:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=jmIsrL21BptfR5lJ33xzvPrHdSqSoSVQqC25q5Isc/M=; b=LGn8ICS8ctZzhVfqCQip2GCoVki9orhRbfsAdo9BI2+KhMOTAsFwf4QfbuqbLNoP/o LdqZ3mQxwtcvePufLvvrBmkYpiBTza7FFI4udnd+jVqq+0R/aVEcEgtjpNfLci/mqone HzqoIEFSyAUFxalwc+xfs/90u1N2rVybxNk8s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=jmIsrL21BptfR5lJ33xzvPrHdSqSoSVQqC25q5Isc/M=; b=tWUxfdppOiFTGE5JRlVYSYGo6zH0fDcH+bOYJ67MXE11gs2R5R98OONTi8lyb22bJ3 i+StqzIRHEjRLdn25DW49g3Q/tLSUH5Yqp20i0oSlv4JHb0hL+/TxWd6vEup1cp0eFCW fVEv7kk4VueHe4D/8dArHFPjkdjwdBHBKXwXDaShgK3pTxDsTeFsW4ABRUpMp3MbMT+Z 56AdPm1ZLLRdrTgccwW+hg9EKz6eFHN+gZ53rV0FuqDtt+e9/yBD6kLCGtsfLs2aiInA +77FvMDBJ4RMztJ00mn2NpikJFLwn+cem61uZsGncmJdRxmArZXvazC8qeJfe6rYaPXA HicQ== X-Gm-Message-State: AOAM531Q2z565ffSNLhBj1SRhpCqCDTSSVC+5n7PRVtvyvnngHckd22W hy8xtEH5lSn1IDGJF7KNd9uNmrLlGqS220vDsL4= X-Received: by 2002:a17:906:7d0d:: with SMTP id u13mr184055ejo.448.1601273856198; Sun, 27 Sep 2020 23:17:36 -0700 (PDT) MIME-Version: 1.0 References: <20200923164730.176881-1-tmaimon77@gmail.com> <20200923164730.176881-2-tmaimon77@gmail.com> In-Reply-To: <20200923164730.176881-2-tmaimon77@gmail.com> From: Joel Stanley Date: Mon, 28 Sep 2020 06:17:21 +0000 Message-ID: Subject: Re: [PATCH v7 1/5] arm: dts: modify NPCM7xx device tree clock parameter To: Tomer Maimon Cc: Rob Herring , Mark Rutland , Avi Fishman , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , devicetree , Linux Kernel Mailing List , OpenBMC Maillist Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 23 Sep 2020 at 16:48, Tomer Maimon wrote: > > Modify NPCM7xx device tree clock parameter to clock constants that > define at include/dt-bindings/clock/nuvoton,npcm7xx-clock.h file. > > Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Tomer, for next time: when sending new versions of a patch series you can add the reviewed-by lines to patches that you have not changed. This one is a good case of that. It saves the reviewer having to go look at it again. Cheers, Joel > --- > arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 19 ++++++++++--------- > arch/arm/boot/dts/nuvoton-npcm750.dtsi | 6 +++--- > 2 files changed, 13 insertions(+), 12 deletions(-) > > diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi > index d2d0761295a4..16a28c5c4131 100644 > --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi > +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi > @@ -3,6 +3,7 @@ > // Copyright 2018 Google, Inc. > > #include > +#include > > / { > #address-cells = <1>; > @@ -80,7 +81,7 @@ > interrupts = ; > cache-unified; > cache-level = <2>; > - clocks = <&clk 10>; > + clocks = <&clk NPCM7XX_CLK_AXI>; > arm,shared-override; > }; > > @@ -120,7 +121,7 @@ > compatible = "nuvoton,npcm750-timer"; > interrupts = ; > reg = <0x8000 0x50>; > - clocks = <&clk 5>; > + clocks = <&clk NPCM7XX_CLK_TIMER>; > }; > > watchdog0: watchdog@801C { > @@ -128,7 +129,7 @@ > interrupts = ; > reg = <0x801C 0x4>; > status = "disabled"; > - clocks = <&clk 5>; > + clocks = <&clk NPCM7XX_CLK_TIMER>; > }; > > watchdog1: watchdog@901C { > @@ -136,7 +137,7 @@ > interrupts = ; > reg = <0x901C 0x4>; > status = "disabled"; > - clocks = <&clk 5>; > + clocks = <&clk NPCM7XX_CLK_TIMER>; > }; > > watchdog2: watchdog@a01C { > @@ -144,13 +145,13 @@ > interrupts = ; > reg = <0xa01C 0x4>; > status = "disabled"; > - clocks = <&clk 5>; > + clocks = <&clk NPCM7XX_CLK_TIMER>; > }; > > serial0: serial@1000 { > compatible = "nuvoton,npcm750-uart"; > reg = <0x1000 0x1000>; > - clocks = <&clk 6>; > + clocks = <&clk NPCM7XX_CLK_UART>; > interrupts = ; > reg-shift = <2>; > status = "disabled"; > @@ -159,7 +160,7 @@ > serial1: serial@2000 { > compatible = "nuvoton,npcm750-uart"; > reg = <0x2000 0x1000>; > - clocks = <&clk 6>; > + clocks = <&clk NPCM7XX_CLK_UART>; > interrupts = ; > reg-shift = <2>; > status = "disabled"; > @@ -168,7 +169,7 @@ > serial2: serial@3000 { > compatible = "nuvoton,npcm750-uart"; > reg = <0x3000 0x1000>; > - clocks = <&clk 6>; > + clocks = <&clk NPCM7XX_CLK_UART>; > interrupts = ; > reg-shift = <2>; > status = "disabled"; > @@ -177,7 +178,7 @@ > serial3: serial@4000 { > compatible = "nuvoton,npcm750-uart"; > reg = <0x4000 0x1000>; > - clocks = <&clk 6>; > + clocks = <&clk NPCM7XX_CLK_UART>; > interrupts = ; > reg-shift = <2>; > status = "disabled"; > diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi > index 6ac340533587..a37bb2294b8f 100644 > --- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi > +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi > @@ -17,7 +17,7 @@ > cpu@0 { > device_type = "cpu"; > compatible = "arm,cortex-a9"; > - clocks = <&clk 0>; > + clocks = <&clk NPCM7XX_CLK_CPU>; > clock-names = "clk_cpu"; > reg = <0>; > next-level-cache = <&l2>; > @@ -26,7 +26,7 @@ > cpu@1 { > device_type = "cpu"; > compatible = "arm,cortex-a9"; > - clocks = <&clk 0>; > + clocks = <&clk NPCM7XX_CLK_CPU>; > clock-names = "clk_cpu"; > reg = <1>; > next-level-cache = <&l2>; > @@ -38,7 +38,7 @@ > reg = <0x3fe600 0x20>; > interrupts = IRQ_TYPE_LEVEL_HIGH)>; > - clocks = <&clk 5>; > + clocks = <&clk NPCM7XX_CLK_AHB>; > }; > }; > }; > -- > 2.22.0 >