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[23.128.96.18]) by mx.google.com with ESMTP id j12si572482ejy.198.2020.09.28.05.56.28; Mon, 28 Sep 2020 05:56:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b="f/uiZ9J2"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726641AbgI1Myo (ORCPT + 99 others); Mon, 28 Sep 2020 08:54:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726424AbgI1Myo (ORCPT ); Mon, 28 Sep 2020 08:54:44 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12DBEC061755; Mon, 28 Sep 2020 05:54:44 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id d4so983285wmd.5; Mon, 28 Sep 2020 05:54:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=rYxYmSPSlKHJNuyTnVmBf92AIgqLsIDS6+bNfIKzBOI=; b=f/uiZ9J2wDYbxzP4nCnLDSCb/JeCxxtL/tewdvYGpcaY1AhOz0TNDO2ya69nfewfbK 4QWnnDa4EIozAwsOnOwzAdX6rewBlqYp5HsdmuP+Yv2MZFix37LxfTnJJYkM/QGlUiwe jeTUiIJV/FJj+n6KNMy6t2xv/BACw9bzhcdtcyz7xHETTHOLX0kNjR31a46lM0pm95uB eca9KBxUHA+y/OJELpA0G+XxzcLzDAVuTSLtHf09UfzHYsXJvfgFIPDUgmmQn3czGVHa mKO2H87kwZyGXdDKxj+pTaxCV9+JXyK1l6gazdQP++Vb6mYqBPUsK9Bi1n5WfXdIFhPi 32MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=rYxYmSPSlKHJNuyTnVmBf92AIgqLsIDS6+bNfIKzBOI=; b=FmsV1D7OPWSyYFSwkCLIJAC7ncPjKufz7mR5tZYiXZVvnRIXteDvADJirp9PioM8km UqL0KA8aJHThPbFrUpiFkmFALYtM7r4ewaAIvtcCfuao/ptUFfrWei9EaivpKDGBUTp5 mWSHDHjqhwxKXGrlgazn+KFzftrYCer3oZK1bbtInlWxvelmXsnsnfQYkbYWegdC4VPF kG7BugMNbHZv5S7zasibRnxFiC+RHrpangsfrNMCErJuBrO3kHn9zC2ZvRHBGBVODRcy xudmmypb6nHWU3Il5J312ypS3z2BUgsfY9SpBj9WEICfKGcy2DaHGnnO371W1X1seHhh S8XA== X-Gm-Message-State: AOAM531OzW1iR/C+acfTlb7TLvVZyChkUjSxr65bqJOs4t+86Jo3VaXr K1+QnSipp2ByE+P+bDRM3NoCXzbUkxA= X-Received: by 2002:a7b:ce89:: with SMTP id q9mr1481722wmj.65.1601297682561; Mon, 28 Sep 2020 05:54:42 -0700 (PDT) Received: from localhost ([217.111.27.204]) by smtp.gmail.com with ESMTPSA id z8sm1415537wrl.11.2020.09.28.05.54.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2020 05:54:41 -0700 (PDT) Date: Mon, 28 Sep 2020 14:54:38 +0200 From: Thierry Reding To: JC Kuo Cc: gregkh@linuxfoundation.org, robh@kernel.org, jonathanh@nvidia.com, kishon@ti.com, linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, nkristam@nvidia.com Subject: Re: [PATCH v3 00/15] Tegra XHCI controller ELPG support Message-ID: <20200928125438.GC3065790@ulmo> References: <20200909081041.3190157-1-jckuo@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="96YOpH+ONegL0A3E" Content-Disposition: inline In-Reply-To: <20200909081041.3190157-1-jckuo@nvidia.com> User-Agent: Mutt/1.14.7 (2020-08-29) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --96YOpH+ONegL0A3E Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Sep 09, 2020 at 04:10:26PM +0800, JC Kuo wrote: > Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated) > state for power saving when all of the connected USB devices are in > suspended state. This patch series includes clk, phy and pmc changes > that are required for properly place controller in ELPG and bring > controller out of ELPG. >=20 > JC Kuo (15): > clk: tegra: Add PLLE HW power sequencer control > clk: tegra: Don't enable PLLE HW sequencer at init Is it safe to apply this second patch before the others have applied? Since we now need to explicitly enable the HW sequencer, it won't be enabled before the corresponding patch does that. So applying patch 2 before the others sounds like it would break existing users of the HW sequencer. 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