Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Mon, 28 Sep 2020 15:08:49 +0200
From:   Thierry Reding <thierry.reding@gmail.com>
To:     JC Kuo <jckuo@nvidia.com>
Cc:     gregkh@linuxfoundation.org, robh@kernel.org, jonathanh@nvidia.com,
        kishon@ti.com, linux-tegra@vger.kernel.org,
        linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, nkristam@nvidia.com
Subject: Re: [PATCH v3 05/15] phy: tegra: xusb: Rearrange UPHY init on
 Tegra210
Message-ID: <20200928130849.GF3065790@ulmo>
References: <20200909081041.3190157-1-jckuo@nvidia.com>
 <20200909081041.3190157-6-jckuo@nvidia.com>
MIME-Version: 1.0
Content-Type: multipart/signed; micalg=pgp-sha256;
        protocol="application/pgp-signature"; boundary="Pgaa2uWPnPrfixyx"
Content-Disposition: inline
In-Reply-To: <20200909081041.3190157-6-jckuo@nvidia.com>
User-Agent: Mutt/1.14.7 (2020-08-29)
Precedence: bulk


--Pgaa2uWPnPrfixyx
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable

On Wed, Sep 09, 2020 at 04:10:31PM +0800, JC Kuo wrote:
> This commit is a preparation for enabling XUSB SC7 support.
> It rearranges Tegra210 XUSB PADCTL UPHY initialization sequence,
> for the following reasons:
>=20
> 1. PLLE hardware power sequencer has to be enabled only after both
>    PEX UPHY PLL and SATA UPHY PLL are initialized.
>    tegra210_uphy_init() -> tegra210_pex_uphy_enable()
>                         -> tegra210_sata_uphy_enable()
>                         -> tegra210_plle_hw_sequence_start()
>                         -> tegra210_aux_mux_lp0_clamp_disable()
>=20
> 2. At cold boot and SC7 exit, the following bits must be cleared after
>    PEX/SATA lanes are out of IDDQ (IDDQ_DISABLE=3D1).
>    a. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN,
>    b. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY
>    c. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN
>=20
>    tegra210_pex_uphy_enable() and tegra210_sata_uphy_enable() are in
>    charge of bringing lanes out of IDDQ, and then AUX_MUX_LP0_* bits
>    will be cleared by tegra210_aux_mux_lp0_clamp_disable().
>=20
> Signed-off-by: JC Kuo <jckuo@nvidia.com>
> ---
> v3:
>    make separate changes
>    use "unsigned int" instead "int" type for PHY index
>    add blank line for better readability
>   =20
>  drivers/phy/tegra/xusb-tegra210.c | 203 +++++++++++++++---------------
>  drivers/phy/tegra/xusb.h          |   4 +-
>  2 files changed, 102 insertions(+), 105 deletions(-)

Acked-by: Thierry Reding <treding@nvidia.com>

--Pgaa2uWPnPrfixyx
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl9x4GEACgkQ3SOs138+
s6GhchAAkPMKilPY4JMW/bvt3MBYK7A1MMaVtO9dLUY52mM1qF9Kfd7gb27GvgOx
8xsT7a6ckgaydc/Mv0Ll/Q0TOm9RTvYSZQYV+I7EXtZYcgujfeR5c1bORiOZZWxc
QIgv+DN7wGcrTf82Z8Tg/eIugt2WPlILY+kmPYDxEF+J3PnH6WufUAIR8osArhhP
pCjZ+5ZrAttBUNJM2tvErCaYHDauxDFN3r6sQqMbo8VchpTh6jW8+nuENaScTHNk
99r3WrJjO3nCVqLWqmQPl4uqg0L+f3VlG6akuGSX8ZeOOqUz+J/MmFsvuTO+j//K
w820awaV8c9TCy14itTtIhQnPG/xybXexZP0lLrKyVpJZdJEonkFjgOe/zt4PeHz
SjEgrzDjc3sdkcK7Dr2QZdQmxYXpK/GcFm/dAMUWXUzhEP+g3Wg5/5Trdpk23cBI
pO/rr2huNIERpsgxRETCom2+SvVI9UYktYEXu78lhgAtSPU6Y3+hJLKLP0XgGFMN
c6Wiwe8GK4AO8KlAB+/iKdhcOn8/dIuc3CZBqndUCURvhnK6D37Fjzyca89i0rzP
DLvKCfuSckh78ZJeg6qkGMzAcEQgVOBCBEavmtIfrgB1Lb/nCdJtosKPSqp7erfK
8ZtxBtOXxnYla9C+QkrJOY1tkZPRtUwlPa0doK3Lndr3cNv+SG8=
=PnVB
-----END PGP SIGNATURE-----

--Pgaa2uWPnPrfixyx--