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[23.128.96.18]) by mx.google.com with ESMTP id a25si647990ejx.145.2020.09.28.07.01.06; Mon, 28 Sep 2020 07:01:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=vDmSUBpY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726567AbgI1N5E (ORCPT + 99 others); Mon, 28 Sep 2020 09:57:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:33886 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726310AbgI1N5E (ORCPT ); Mon, 28 Sep 2020 09:57:04 -0400 Received: from mail-oi1-f179.google.com (mail-oi1-f179.google.com [209.85.167.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5629821D7F; Mon, 28 Sep 2020 13:57:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601301423; bh=jpy86xlaUGPlUxTUN9/FT28T6TJmY9Ad8uRAhplOiLM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=vDmSUBpYh7JEkaKpuSJodZASpvn5qYNR9WD7Zz+ui1FtxvuddwJe0WaOjmp/axHLo CvGi+htN93Dw+bCHcooMeEmLM6ROMwqzptJbER2UAJzI5Gc0Rbgm9qtlYuoiCTp2kJ kSRDYEYKPRHzv/MBnvBvucpR9bEchfKfyRLFlTYk= Received: by mail-oi1-f179.google.com with SMTP id i17so1368230oig.10; Mon, 28 Sep 2020 06:57:03 -0700 (PDT) X-Gm-Message-State: AOAM533YkebO7Em65jlKwaInsqvecp/1Izm6K5dwseVO26IlCjuIwbxh 6leaTj1LaaOHGON5YRlfpSw362VOLmMmtn0Mtg== X-Received: by 2002:aca:7543:: with SMTP id q64mr978362oic.147.1601301422618; Mon, 28 Sep 2020 06:57:02 -0700 (PDT) MIME-Version: 1.0 References: <20200916081831.24747-1-ran.wang_1@nxp.com> <20200923023234.GA3751572@bogus> In-Reply-To: From: Rob Herring Date: Mon, 28 Sep 2020 08:56:51 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/5] Documentation: dt: binding: fsl: Add 'fsl,ippdexpcr1-alt-addr' property To: Ran Wang Cc: Leo Li , Shawn Guo , "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Biwen Li Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 23, 2020 at 1:44 AM Ran Wang wrote: > > Hi Rob, > > On Wednesday, September 23, 2020 10:33 AM, Rob Herring wrote: > > > > On Wed, Sep 16, 2020 at 04:18:27PM +0800, Ran Wang wrote: > > > From: Biwen Li > > > > > > The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata > > > A-008646 on LS1021A > > > > > > Signed-off-by: Biwen Li > > > Signed-off-by: Ran Wang > > > --- > > > Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19 > > > +++++++++++++++++++ > > > 1 file changed, 19 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt > > > b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt > > > index 5a33619..1be58a3 100644 > > > --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt > > > +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt > > > @@ -34,6 +34,11 @@ Chassis Version Example Chips > > > Optional properties: > > > - little-endian : RCPM register block is Little Endian. Without it RCPM > > > will be Big Endian (default case). > > > + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue > > > + on SoC LS1021A and only needed on SoC LS1021A. > > > + Must include 2 entries: > > > + The first entry must be a link to the SCFG device node. > > > + The 2nd entry must be offset of register IPPDEXPCR1 in SCFG. > > > > You don't need a DT change for this. You can find SCFG node by its compatible > > string and then the offset should be known given this issue is only on 1 SoC. > > Did you mean that RCPM driver just to access IPPDEXPCR1 shadowed register in SCFG > directly without fetching it's offset info. from DT? Yes. There's only 1 possible value of the offset because there's only one SoC, so the driver can hardcode the offset. And I assume there's only one SCFG node, so you can find it by its compatible string (of_find_compatible_node). Rob