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From:   Ansuel Smith <ansuelsmth@gmail.com>
To:     Rob Herring <robh+dt@kernel.org>
Cc:     Ansuel Smith <ansuelsmth@gmail.com>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        MyungJoo Ham <myungjoo.ham@samsung.com>,
        Kyungmin Park <kyungmin.park@samsung.com>,
        Chanwoo Choi <cw00.choi@samsung.com>,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org
Subject: [PATCH v2 2/2] dt-bindings: arm: Document L2 Krait CPU Cache scaling driver
Date:   Tue, 29 Sep 2020 18:29:25 +0200
Message-Id: <20200929162926.139-2-ansuelsmth@gmail.com>
In-Reply-To: <20200929162926.139-1-ansuelsmth@gmail.com>
References: <20200929162926.139-1-ansuelsmth@gmail.com>
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Document dedicated L2 Krait CPU Cache devfreq scaling driver.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
v2:
* Fix problems reported by Rob
* Update example to use opp v2
* Drop unused voltage-tollerance
* Better describe scaling thresholds
* Add bindings to describe Krait L2-Cache

 .../bindings/arm/qcom,krait-cache.yaml        | 116 ++++++++++++++++++
 1 file changed, 116 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache.yaml

diff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache.yaml b/Documentation/devicetree/bindings/arm/qcom,krait-cache.yaml
new file mode 100644
index 000000000000..4143a758dc28
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/qcom,krait-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Krait L2 CPU Cache
+
+maintainers:
+  - Ansuel Smith <ansuelsmth@gmail.com>
+
+description: |
+  This describe all the needed bindings required by the Krait L2 CPU Cache.
+
+  Describe what level is available for the shared cache connected to the
+  Krait Cpus, the qcom saw used for qcom spm and how the cache should be
+  scaled using operating-points and cpufreq thresholds.
+  The Krait L2 CPU Cache Scaling Driver scale the frequency and optionally
+  voltage when the Cpu Frequency is changed (using the cpufreq notifier).
+
+  Cache is scaled with the max frequency across all CPU core and the Cache
+  frequency will scale based on the configured CpuFreq threshold in the dts.
+  (example: CPU 600000 kHz, L2 Cache will be scaled to 1000000000 Hz.
+            CPU 1100000 kHz, L2 Cache will be scaled to 1000000000 Hz.
+            CPU 1200000 KHz, L2 Cache will be scaled to 1200000000 Hz.)
+
+  The CpuFreq thresholds can be set from a minimum of 3 bin (idle, nominal
+  and high) and upper but the Krait Cache supports only 3 operating points.
+
+properties:
+  compatible:
+    const: qcom,krait-cache
+
+  cache-level:
+    const: 2
+
+  qcom,saw:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+    description: |
+      Specifies the SAW* node associated with this L2 Cache.
+
+      Required for systems that have an "enable-method" property
+      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" defined in
+      CPUs node.
+
+      * arm/msm/qcom,saw2.txt
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: l2
+
+  qcom,l2-cpufreq:
+    description: |
+      Threshold used by the driver to scale the L2 cache.
+      If the max CPU Frequency is more than the set frequency,
+      the driver will transition to the next frequency bin.
+      Value is in kHz
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 3
+    items:
+      - description: idle
+      - description: nominal
+      - description: high
+
+  l2-supply:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+    description: Phandle to the L2 regulator supply.
+
+  operating-points-v2: true
+
+required:
+  - compatible
+  - cache-level
+  - qcom,saw
+  - clocks
+  - clock-names
+  - qcom,l2-cpufreq
+
+examples:
+  - |
+    L2: l2-cache {
+      compatible = "qcom,krait-cache";
+      cache-level = <2>;
+      qcom,saw = <&saw_l2>;
+
+      clocks = <&kraitcc 4>;
+      clock-names = "l2";
+      l2-supply = <&smb208_s1a>;
+      qcom,l2-cpufreq = <384000 600000 1200000>;
+      operating-points-v2 = <&opp_table_l2>;
+    };
+
+    opp_table_l2: opp_table_l2 {
+      compatible = "operating-points-v2";
+
+      opp-384000000 {
+        opp-hz = /bits/ 64 <384000000>;
+        opp-microvolt = <1100000>;
+        clock-latency-ns = <100000>;
+      };
+
+      opp-1000000000 {
+        opp-hz = /bits/ 64 <1000000000>;
+        opp-microvolt = <1100000>;
+        clock-latency-ns = <100000>;
+      };
+
+      opp-1200000000 {
+        opp-hz = /bits/ 64 <1200000000>;
+        opp-microvolt = <1150000>;
+        clock-latency-ns = <100000>;
+      };
+    };
-- 
2.27.0