Received: by 2002:a05:6a10:22f:0:0:0:0 with SMTP id 15csp4424349pxk; Wed, 30 Sep 2020 02:34:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFpiXAYu7gbm0YlFXfZpwH8+DS5yvYzEdSaK3Qmei1eynUG7zBurg1gkM5T2HJWAhaaJgJ X-Received: by 2002:a17:906:1909:: with SMTP id a9mr1809973eje.127.1601458447322; Wed, 30 Sep 2020 02:34:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601458447; cv=none; d=google.com; s=arc-20160816; b=EFBrpRuzjUJkH4dod0jd8WjqcZ81shCzbl/itM+QGHVZi/sHR23UZAis9fObmIxCGI Is8HT2m26sp11MWQsmeRhGPMJoOr55DQOw0pFWbVdfhUnDvH1t/sTIEWbLc74iQQ/Ytb K1tA/kLkxWRxdcQ03aMR8ZA72UTvM+whEzcEHDycJc3FM9wFd2uRJdXGxR1DGVrKMFcE By/KiiLjki2hT4olVyyWtyixIetCSJISMWwav6pNovhtTjWE/Nbeifp9k2PrBg9asexI zGwTFYOus0sjM2TgrbyXePqrhcZWTbBYIPu5I0arTvo8ZghTOcpGx811ei+fg3wKrzAV qlkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=U5m05sO4egjv1zijxBef+3GauunkLrRv2hfw19S5vl8=; b=PueqCheH2a0qMLGhMn8jO+EtdKYNPUbXMsKHizXBwMYK3m70bckxK09vFjahJHS3so dOhTd8a42dCJ+jXC52crKv7WXWC9O1d4DveuUCXmyWvEFr4RS7si1DwUreY96Q2nuL8r pwnjveYbHiYf4QBonWroAZBYvcS3lgjDutMUQzMZeZzNpkpI1OkdJ3xn30KsMkbhufsa jntgeF4zRwXGPAVcMQKegzX+IKlbk5fwX36+bABo9MrbfFnEshoEl7hcd6ANqU7Tr1qQ sWgvKwBGgf+6itvu42hwgyJ7q/3OHm8Ibx6TA8/lC8hN3tcnPMnhTIdjhxyFnzz1oGqq CVzQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a21si616013eds.368.2020.09.30.02.33.44; Wed, 30 Sep 2020 02:34:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728851AbgI3Jbw (ORCPT + 99 others); Wed, 30 Sep 2020 05:31:52 -0400 Received: from foss.arm.com ([217.140.110.172]:60818 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725776AbgI3Jbw (ORCPT ); Wed, 30 Sep 2020 05:31:52 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E493AD6E; Wed, 30 Sep 2020 02:31:51 -0700 (PDT) Received: from bogus (unknown [10.57.47.250]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E8B1D3F70D; Wed, 30 Sep 2020 02:31:46 -0700 (PDT) Date: Wed, 30 Sep 2020 10:29:54 +0100 From: Sudeep Holla To: Ansuel Smith Cc: Rob Herring , Andy Gross , Bjorn Andersson , MyungJoo Ham , Kyungmin Park , Sudeep Holla , Chanwoo Choi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: Re: [PATCH v2 1/2] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver Message-ID: <20200930092954.GA7125@bogus> References: <20200929162926.139-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200929162926.139-1-ansuelsmth@gmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 29, 2020 at 06:29:24PM +0200, Ansuel Smith wrote: > Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually > scale the Cache frequency when the CPU frequency is changed. This > devfreq driver register with the cpu notifier and scale the Cache > based on the max Freq across all core as the CPU cache is shared across > all of them. If provided this also scale the voltage of the regulator > attached to the CPU cache. The scaling logic is based on the CPU freq > and the 3 scaling interval are set by the device dts. > I have raised this concern before. I am worried this kind of independent CPU and cache frequency controls make way for clkscrew kind of attacks. Why can't the clocks be made parent/child or secondary and automatically updated when CPU clocks are changed. -- Regards, Sudeep