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Wed, 30 Sep 2020 23:14:13 -0700 (PDT) MIME-Version: 1.0 References: <20200930083120.11971-1-wenbin.mei@mediatek.com> <20200930083120.11971-5-wenbin.mei@mediatek.com> In-Reply-To: <20200930083120.11971-5-wenbin.mei@mediatek.com> From: Nicolas Boichat Date: Thu, 1 Oct 2020 14:14:02 +0800 Message-ID: Subject: Re: [PATCH v3 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc To: Wenbin Mei Cc: Ulf Hansson , Rob Herring , Chaotian Jing , Matthias Brugger , linux-mmc@vger.kernel.org, Devicetree List , linux-arm Mailing List , "moderated list:ARM/Mediatek SoC support" , lkml , srv_heupstream Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 30, 2020 at 4:31 PM Wenbin Mei wrote: > > MT8192 msdc is an independent sub system, we need control more bus > clocks for it. > Add support for the additional subsys clocks to allow it to be > configured appropriately. > > Signed-off-by: Wenbin Mei > --- > drivers/mmc/host/mtk-sd.c | 77 ++++++++++++++++++++++++++++++--------- > 1 file changed, 59 insertions(+), 18 deletions(-) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index a704745e5882..9a1422955593 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -425,6 +425,8 @@ struct msdc_host { > struct clk *h_clk; /* msdc h_clk */ > struct clk *bus_clk; /* bus clock which used to access register */ > struct clk *src_clk_cg; /* msdc source clock control gate */ > + struct clk *sys_clk_cg; /* msdc subsys clock control gate */ > + struct clk_bulk_data bulk_clks[3]; /* pclk, axi, ahb clock control gate */ > u32 mclk; /* mmc subsystem clock frequency */ > u32 src_clk_freq; /* source clock frequency */ > unsigned char timing; > @@ -784,6 +786,8 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) > > static void msdc_gate_clock(struct msdc_host *host) > { > + clk_bulk_disable_unprepare(ARRAY_SIZE(host->bulk_clks), > + host->bulk_clks); > clk_disable_unprepare(host->src_clk_cg); > clk_disable_unprepare(host->src_clk); > clk_disable_unprepare(host->bus_clk); > @@ -792,10 +796,17 @@ static void msdc_gate_clock(struct msdc_host *host) > > static void msdc_ungate_clock(struct msdc_host *host) > { > + int ret; > + > clk_prepare_enable(host->h_clk); > clk_prepare_enable(host->bus_clk); > clk_prepare_enable(host->src_clk); > clk_prepare_enable(host->src_clk_cg); > + ret = clk_bulk_prepare_enable(ARRAY_SIZE(host->bulk_clks), > + host->bulk_clks); > + if (ret) > + dev_dbg(host->dev, "enable clks failed!\n"); dev_err looks a lot more appropriate. Also, don't you want to exit the function in that case, rather than going to the while loop below where you may get stuck? > + > while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) > cpu_relax(); > } > @@ -2366,6 +2377,52 @@ static void msdc_of_property_parse(struct platform_device *pdev, > host->cqhci = false; > } > > +static int msdc_of_clock_parse(struct platform_device *pdev, > + struct msdc_host *host) > +{ > + struct clk *clk; > + > + host->src_clk = devm_clk_get(&pdev->dev, "source"); > + if (IS_ERR(host->src_clk)) > + return PTR_ERR(host->src_clk); > + > + host->h_clk = devm_clk_get(&pdev->dev, "hclk"); > + if (IS_ERR(host->h_clk)) > + return PTR_ERR(host->h_clk); > + > + host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); > + if (IS_ERR(host->bus_clk)) > + host->bus_clk = NULL; Use devm_clk_get_optional instead (ditto for the next 2). > + > + /*source clock control gate is optional clock*/ > + host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); > + if (IS_ERR(host->src_clk_cg)) > + host->src_clk_cg = NULL; > + > + host->sys_clk_cg = devm_clk_get(&pdev->dev, "sys_cg"); > + if (IS_ERR(host->sys_clk_cg)) > + host->sys_clk_cg = NULL; > + else > + clk_prepare_enable(host->sys_clk_cg); This doesn't need to be in an else branch, calling clk_prepare_enable on a NULL clock is fine. However, is it expected that this clock is turned on forever after probe?! At the very least, the clock should be disabled in msdc_drv_remove, but, really, I think it should be enabled as needed, like the other clocks, in msdc_gate_clock? > + > + clk = devm_clk_get(&pdev->dev, "pclk_cg"); > + if (IS_ERR(clk)) > + clk = NULL; > + host->bulk_clks[0].clk = clk; > + > + clk = devm_clk_get(&pdev->dev, "axi_cg"); > + if (IS_ERR(clk)) > + clk = NULL; > + host->bulk_clks[1].clk = clk; > + > + clk = devm_clk_get(&pdev->dev, "ahb_cg"); > + if (IS_ERR(clk)) > + clk = NULL; > + host->bulk_clks[2].clk = clk; Use devm_clk_bulk_get_optional for these 3. > + > + return 0; > +} > + > static int msdc_drv_probe(struct platform_device *pdev) > { > struct mmc_host *mmc; > @@ -2405,25 +2462,9 @@ static int msdc_drv_probe(struct platform_device *pdev) > if (ret) > goto host_free; > > - host->src_clk = devm_clk_get(&pdev->dev, "source"); > - if (IS_ERR(host->src_clk)) { > - ret = PTR_ERR(host->src_clk); > - goto host_free; > - } > - > - host->h_clk = devm_clk_get(&pdev->dev, "hclk"); > - if (IS_ERR(host->h_clk)) { > - ret = PTR_ERR(host->h_clk); > + ret = msdc_of_clock_parse(pdev, host); > + if (ret) > goto host_free; > - } > - > - host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); > - if (IS_ERR(host->bus_clk)) > - host->bus_clk = NULL; > - /*source clock control gate is optional clock*/ > - host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); > - if (IS_ERR(host->src_clk_cg)) > - host->src_clk_cg = NULL; > > host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, > "hrst"); > -- > 2.18.0