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[23.128.96.18]) by mx.google.com with ESMTP id i22si3937142ejy.5.2020.10.01.12.08.21; Thu, 01 Oct 2020 12:08:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=PJO6T9Ov; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732967AbgJATGY (ORCPT + 99 others); Thu, 1 Oct 2020 15:06:24 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55802 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733025AbgJATGV (ORCPT ); Thu, 1 Oct 2020 15:06:21 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 091J6EF0130925; Thu, 1 Oct 2020 14:06:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1601579174; bh=4hsgccja69xkA6Nqz2du8sVQOfenw3Ib088cYiElafE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PJO6T9OvxkIDlghz6IYhBBwahnmPlvX7wXAsBfeRg2d2YJfRoYi9TyJe5kHkSqhDf IwKVFwW9fAL8xXaseYJTsM9HWjh/cBKjbFbUTyVkNFXUg/4ttN3Nq4HU9veDX7GHoG o08eUgMIm4zIh6XdUuY4wxVRsLlxSXYo5HFbF+10= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 091J6ERZ043132 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 Oct 2020 14:06:14 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 1 Oct 2020 14:06:14 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 1 Oct 2020 14:06:14 -0500 Received: from a0230074-Latitude-E7470.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 091J5gYq070134; Thu, 1 Oct 2020 14:06:10 -0500 From: Faiz Abbas To: , , CC: , , , , Subject: [PATCH 5/8] arm64: dts: ti: k3-j721e-common-proc-board: Add support SD card UHS modes Date: Fri, 2 Oct 2020 00:35:38 +0530 Message-ID: <20201001190541.6364-6-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201001190541.6364-1-faiz_abbas@ti.com> References: <20201001190541.6364-1-faiz_abbas@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for UHS modes for the SD card connected at sdhci1. This involves adding regulators for voltage switching and power cycling the SD card and removing the no-1-8-v property. Signed-off-by: Faiz Abbas --- .../dts/ti/k3-j721e-common-proc-board.dts | 35 ++++++++++++++++++- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 -- 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 52e121155563..0df9e6117b7c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -67,6 +67,31 @@ regulator-boot-on; }; + vdd_mmc1: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv_alt: gpio-regulator-TLV71033 { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; + regulator-name = "tlv71033"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0 + 3300000 0x1>; + }; + sound0: sound@0 { compatible = "ti,j721e-cpb-audio"; model = "j721e-cpb"; @@ -106,7 +131,13 @@ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ + >; + }; + + main_usbss0_pins_default: main_usbss0_pins_default { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ @@ -295,6 +326,8 @@ &main_sdhci1 { /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 630b195cbc8a..a38d772b8356 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1109,7 +1109,6 @@ ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; - no-1-8-v; }; main_sdhci2: sdhci@4f98000 { @@ -1130,7 +1129,6 @@ ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; - no-1-8-v; }; usbss0: cdns-usb@4104000 { -- 2.17.1