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Subject: Re: [PATCH v3 01/18] irqchip: Add IMS (Interrupt Message Storage)
 driver
To:     Thomas Gleixner <tglx@linutronix.de>,
        Dave Jiang <dave.jiang@intel.com>, vkoul@kernel.org,
        maz@kernel.org, bhelgaas@google.com, alex.williamson@redhat.com,
        jacob.jun.pan@intel.com, ashok.raj@intel.com, jgg@mellanox.com,
        yi.l.liu@intel.com, baolu.lu@intel.com, kevin.tian@intel.com,
        sanjay.k.kumar@intel.com, tony.luck@intel.com, jing.lin@intel.com,
        dan.j.williams@intel.com, kwankhede@nvidia.com,
        eric.auger@redhat.com, parav@mellanox.com, rafael@kernel.org,
        netanelg@mellanox.com, shahafs@mellanox.com,
        yan.y.zhao@linux.intel.com, pbonzini@redhat.com,
        samuel.ortiz@intel.com, mona.hossain@intel.com
Cc:     dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
        x86@kernel.org, linux-pci@vger.kernel.org, kvm@vger.kernel.org
References: <160021207013.67751.8220471499908137671.stgit@djiang5-desk3.ch.intel.com>
 <160021246221.67751.16280230469654363209.stgit@djiang5-desk3.ch.intel.com>
 <87362zi0nr.fsf@nanos.tec.linutronix.de>
From:   "Dey, Megha" <megha.dey@intel.com>
Message-ID: <dd1c34c5-e2c0-25fc-b668-a5bbb7869397@intel.com>
Date:   Thu, 1 Oct 2020 15:59:24 -0700
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Hi Thomas,

On 9/30/2020 11:23 AM, Thomas Gleixner wrote:
> On Tue, Sep 15 2020 at 16:27, Dave Jiang wrote:
>> From: Thomas Gleixner <tglx@linutronix.de>
>> +config IMS_MSI_ARRAY
>> +	bool "IMS Interrupt Message Storm MSI controller for device memory storage arrays"
> Hehe, you missed a Message Storm :)
i will change this in the next version
>> +	depends on PCI
>> +	select IMS_MSI
>> +	select GENERIC_MSI_IRQ_DOMAIN
>> +	help
>> +	  Support for IMS Interrupt Message Storm MSI controller
> and another one.
ok :)
>
>> +	  with IMS slot storage in a slot array in device memory
>> +
>> +static void ims_array_mask_irq(struct irq_data *data)
>> +{
>> +	struct msi_desc *desc = irq_data_get_msi_desc(data);
>> +	struct ims_slot __iomem *slot = desc->device_msi.priv_iomem;
>> +	u32 __iomem *ctrl = &slot->ctrl;
>> +
>> +	iowrite32(ioread32(ctrl) | IMS_VECTOR_CTRL_MASK, ctrl);
>> +	ioread32(ctrl); /* Flush write to device */
> Bah, I fundamentaly hate tail comments. They are a distraction and
> disturb the reading flow. Put it above the ioread32() please.
Will do.
>
>> +static void ims_array_unmask_irq(struct irq_data *data)
>> +{
>> +	struct msi_desc *desc = irq_data_get_msi_desc(data);
>> +	struct ims_slot __iomem *slot = desc->device_msi.priv_iomem;
>> +	u32 __iomem *ctrl = &slot->ctrl;
>> +
>> +	iowrite32(ioread32(ctrl) & ~IMS_VECTOR_CTRL_MASK, ctrl);
> Why is this one not flushed?
I will add it.
>
>> +}
>> +
>> +static void ims_array_write_msi_msg(struct irq_data *data, struct msi_msg *msg)
>> +{
>> +	struct msi_desc *desc = irq_data_get_msi_desc(data);
>> +	struct ims_slot __iomem *slot = desc->device_msi.priv_iomem;
>> +
>> +	iowrite32(msg->address_lo, &slot->address_lo);
>> +	iowrite32(msg->address_hi, &slot->address_hi);
>> +	iowrite32(msg->data, &slot->data);
>> +	ioread32(slot);
> Yuck? slot points to the struct and just because ioread32() accepts a
> void pointer does not make it any more readable.
hmm ok , will change this.
>
>> +static void ims_array_reset_slot(struct ims_slot __iomem *slot)
>> +{
>> +	iowrite32(0, &slot->address_lo);
>> +	iowrite32(0, &slot->address_hi);
>> +	iowrite32(0, &slot->data);
>> +	iowrite32(0, &slot->ctrl);
> Flush?

ok!

-Megha

>
> Thanks,
>
>          tglx