Received: by 2002:a05:6a10:22f:0:0:0:0 with SMTP id 15csp3124828pxk; Mon, 5 Oct 2020 01:27:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRmJTJS9+/krIHG1QOu9aCwJ77MC9s4NWVnFBtg6rstyxc2A9+HWepAlBT6IAUVZl/CUiL X-Received: by 2002:a50:fa89:: with SMTP id w9mr503945edr.235.1601886473857; Mon, 05 Oct 2020 01:27:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601886473; cv=none; d=google.com; s=arc-20160816; b=ndCmQafV0DHfBeLEVBi4j2J9oaUul0Z+fa1YIgXOdeA4kH/T6cGWyHj9dvzqHciD+j 7ePfF8XVDXdtDwodKdiElEAsdwYfOvYkNZ5Q29mjiyJk99EmKcM2yJqYTjYh9czbxob1 IX0bNCywAg/uwvhAnfCKOi6wNA+etxFygPgVA6i+j5NYcauIv9h/wC1l12afI+OOJwQL KqNL+eGNGl65VGxsD5cuOEOBRPC8J1poxShof5TrTiaw/Uy75GQAqCzJIB2Uo+Ei3s9D YHSIfHAz/pGwEpfJp1yEb9xnT1mpCmKa/K0SKHGNqbu0VTT67qHVvWsxcYTwKHe8ZgnI 4ZHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=sgZX0CSQSkAx/FW8NJOKyPpcaw5lepotpcpZ+fYNql4=; b=hISrd5M3VG6co11M52HcJZwbetOt9N8q1jJZRT4B2kE+VgojT7tqoIpZunfbmoe4Uv lafntDgiWLvK+5aWlvprWx/EsaKFoQ2o9/CzWoFeTBLveRIttnLaCMfJd7OUiaxiClYq ozXSOAJ26esDTxr+S5/zkVKQgiPbh6neT8dsMZVC0hs75mSTw9NdjMHJl+5AYJ1t4X6r mtGiiRA398Qsrh70Vimako7YQVYQuHUtpX3bfq7cTgVS+3e4t1rUt6cQe5Os9uYbxWgM e+dCJcjtsxSH+moDgUgD9e0PYhNC66KCInvRQL5eJpQvg3umeHeiUjyLjUH6AiwKWhzU PyEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@infradead.org header.s=casper.20170209 header.b=f+lVv+3n; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 20si6997055ejx.79.2020.10.05.01.27.31; Mon, 05 Oct 2020 01:27:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=casper.20170209 header.b=f+lVv+3n; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725910AbgJEIZ2 (ORCPT + 99 others); Mon, 5 Oct 2020 04:25:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725891AbgJEIZ1 (ORCPT ); Mon, 5 Oct 2020 04:25:27 -0400 Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:8b0:10b:1236::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BFD5C0613CE for ; Mon, 5 Oct 2020 01:25:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=sgZX0CSQSkAx/FW8NJOKyPpcaw5lepotpcpZ+fYNql4=; b=f+lVv+3nk6I61cyD3Mc3w+xOF6 AX6hYon0CglN9NnSHz22RQ9ij9uXFbxpnFzPL4w+3qcvCAEWkvb9zH/iV32OQmeSV/lt9z4iGGyes BPhkyYi/4AlRQYUfMnax6KIWS+y2urTACgdt6Xmsrzk+SydBt2s+luYFhbO9GLHOlQOt8z9GGX1D3 EjawhYh1h5ISFSkdAInR5SOIqPUWb5qSdyAjxVJ2ygHPVdXxXoTwtT+xvR+s8OvGI1YA1xnoGNJe+ SAZYH2Pc8U24S5T4OFU1vt+yKT+Dt6b3PhouVEc1hiTOMbDLSHlXl6Qq46lsENgqqDYHB22l7W6SO /Z4QgCOw==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPLo6-00087G-6D; Mon, 05 Oct 2020 08:25:20 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 1E0BC300B22; Mon, 5 Oct 2020 10:25:16 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id C34282010461A; Mon, 5 Oct 2020 10:25:16 +0200 (CEST) Date: Mon, 5 Oct 2020 10:25:16 +0200 From: Peter Zijlstra To: Kim Phillips Cc: "Liang, Kan" , mingo@redhat.com, linux-kernel@vger.kernel.org, ak@linux.intel.com Subject: [PATCH] perf/x86: Fix n_pair for cancelled txn Message-ID: <20201005082516.GG2628@hirez.programming.kicks-ass.net> References: <20200930142935.13482-1-kan.liang@linux.intel.com> <20201002110258.GV2628@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 02, 2020 at 04:10:42PM -0500, Kim Phillips wrote: > Tested-by: Kim Phillips --- Subject: perf/x86: Fix n_pair for cancelled txn From: Peter Zijlstra Date: Mon Oct 5 10:09:06 CEST 2020 Kan reported that n_metric gets corrupted for cancelled transactions; a similar issue exists for n_pair for AMD's Large Increment thing. The problem was confirmed and confirmed fixed by Kim using: sudo perf stat -e "{cycles,cycles,cycles,cycles}:D" -a sleep 10 & # should succeed: sudo perf stat -e "{fp_ret_sse_avx_ops.all}:D" -a workload # should fail: sudo perf stat -e "{fp_ret_sse_avx_ops.all,fp_ret_sse_avx_ops.all,cycles}:D" -a workload # previously failed, now succeeds with this patch: sudo perf stat -e "{fp_ret_sse_avx_ops.all}:D" -a workload Fixes: 5738891229a2 ("perf/x86/amd: Add support for Large Increment per Cycle Events") Reported-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Tested-by: Kim Phillips --- arch/x86/events/core.c | 6 +++++- arch/x86/events/perf_event.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1089,8 +1089,10 @@ static int collect_event(struct cpu_hw_e return -EINVAL; cpuc->event_list[n] = event; - if (is_counter_pair(&event->hw)) + if (is_counter_pair(&event->hw)) { cpuc->n_pair++; + cpuc->n_txn_pair++; + } return 0; } @@ -2062,6 +2064,7 @@ static void x86_pmu_start_txn(struct pmu perf_pmu_disable(pmu); __this_cpu_write(cpu_hw_events.n_txn, 0); + __this_cpu_write(cpu_hw_events.n_txn_pair, 0); } /* @@ -2087,6 +2090,7 @@ static void x86_pmu_cancel_txn(struct pm */ __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); + __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair)); perf_pmu_enable(pmu); } --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -235,6 +235,7 @@ struct cpu_hw_events { they've never been enabled yet */ int n_txn; /* the # last events in the below arrays; added in the current transaction */ + int n_txn_pair; int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ u64 tags[X86_PMC_IDX_MAX];