Received: by 2002:a05:6a10:22f:0:0:0:0 with SMTP id 15csp3213854pxk; Mon, 5 Oct 2020 04:19:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwpqjj2OoNCuhozaC5LDb0XMjUXY8EG6UldwOjCZKxzmw5GP1DdwmGAknOA+ZnJ9gYGZs97 X-Received: by 2002:a17:906:6c82:: with SMTP id s2mr15520284ejr.182.1601896743999; Mon, 05 Oct 2020 04:19:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601896743; cv=none; d=google.com; s=arc-20160816; b=XoaN2iE0hOSTkS6q2P8WqC6vMZnvpqyWHIe5eV+L/fzwu1KG8G5GH24Kj2N+OAAlhZ 2l272KlOT91hF0IStiy08O1gkKMH7ACh1xWUNk7n9JrOwVXRIG2Sq76eFpp1j8N0IgZ0 FJNiEZWhXtKXwqqg96JY0CptK62cao8v5Letma8ELQCLsTAPy9Rp2it+ayaEMDy6kdt4 qOH9SYBfggR13YeJjNoQ59mh9cLHMfEr4P72f5naiJJ8Up2OeoFNqG4hmQ3xGQ8Rr185 LCDxHC0SOPrD0HraCTq96NvP1i8JUr/S0MjC+AX2X4YcpPGusiUZ+daFRpraxswG73qY jPWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bYzVAEPg+T7no2D4zqoSLHyRcUTE2Pq7OahtMOxdJ1c=; b=eKbl9Cn5es9cyIORvFhLPZEWayPp4TKuPNR7sS3oy+bKRdiqteyVjj2oRse2WgeCqN c2eU37Idu/HCnyOIuyabQSdrOlnjac6MwVBmrnu/1tHnKsM610TbdGQNp7AmulB61S55 19tzCnMj9sqjodo/l81rufmFccDIJwce+Nwp1Q/TYSjKET5r0Gynlwrvwh3zAhpFJalz Q1XF0402Gge4wzibEq69W5I7vKujtUIwyf7+U2O186lffxz2UP/vjH/uDBPTaQBmFV1w i++ySEE7z+c9mvehU+QseBAWSDY8+r745Vn9aWv55v6Q3BNxEWsnlkZ7AwKwLYpos+S5 OYMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b="02OyK/5e"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v19si6596383ejf.257.2020.10.05.04.18.41; Mon, 05 Oct 2020 04:19:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b="02OyK/5e"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726217AbgJELPG (ORCPT + 99 others); Mon, 5 Oct 2020 07:15:06 -0400 Received: from mail.kernel.org ([198.145.29.99]:57782 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726123AbgJELPB (ORCPT ); Mon, 5 Oct 2020 07:15:01 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BF8412085B; Mon, 5 Oct 2020 11:15:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601896500; bh=QZDBQPDjGlcETLhVySdcVslA4fGitGz/5JwUVeEL0kw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=02OyK/5eMBScjHBMNFvMqBGkA6OMu3pk1ZoyshClgFx4nVejZpHfyPoipDjvR3hMD VsWK7kWg0G64G10iyd5a+IbHGf3q3cQOcWRfJ9bmI/03jPEddxn9enqTe+SafYtzQG wBj1oYj4dg3Cb/5rcY8ehb3bGEXTP4bV6E+GSFSw= Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kPOSJ-00HLMq-7o; Mon, 05 Oct 2020 12:14:59 +0100 From: Marc Zyngier To: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Thierry Reding , Jonathan Hunter , Dmitry Osipenko , Sowjanya Komatineni , Venkat Reddy Talla , Thomas Gleixner , kernel-team@android.com Subject: [PATCH 3/3] soc/tegra: pmc: Don't create fake interrupt hierarchy levels Date: Mon, 5 Oct 2020 12:14:43 +0100 Message-Id: <20201005111443.1390096-4-maz@kernel.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201005111443.1390096-1-maz@kernel.org> References: <20201005111443.1390096-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thierry.reding@gmail.com, jonathanh@nvidia.com, digetx@gmail.com, skomatineni@nvidia.com, vreddytalla@nvidia.com, tglx@linutronix.de, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Tegra PMC driver does ungodly things with the interrupt hierarchy, repeatedly corrupting it by pulling hwirq numbers out of thin air, overriding existing IRQ mappings and changing the handling flow of unsuspecting users. All of this is done in the name of preserving the interrupt hierarchy even when these levels do not exist in the HW. Together with the use of proper IRQs for IPIs, this leads to an unbootable system as the rescheduling IPI gets repeatedly repurposed for random drivers... Instead, let's allow the hierarchy to be trimmed to the level that actually makes sense for the HW, and not any deeper. This avoids having unnecessary callbacks, overriding mappings, and otherwise keeps the hierarchy sane. Signed-off-by: Marc Zyngier --- drivers/soc/tegra/pmc.c | 79 +++++++++++++++-------------------------- 1 file changed, 29 insertions(+), 50 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 9960f7c18431..4eea3134fb3e 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -1993,6 +1993,30 @@ static int tegra_pmc_irq_translate(struct irq_domain *domain, return 0; } +/* Trim the irq hierarchy from a particular irq domain */ +static void trim_hierarchy(unsigned int virq, struct irq_domain *domain) +{ + struct irq_data *tail, *irq_data = irq_get_irq_data(virq); + + /* The PMC doesn't generate any interrupt by itself */ + if (WARN_ON(!irq_data->parent_data)) + return; + + /* Skip until we find the right domain */ + while (irq_data->parent_data && irq_data->parent_data->domain != domain) + irq_data = irq_data->parent_data; + + /* Sever the inner part of the hierarchy... */ + tail = irq_data->parent_data; + irq_data->parent_data = NULL; + + /* ... and free it */ + for (irq_data = tail; irq_data; irq_data = tail) { + tail = irq_data->parent_data; + kfree(irq_data); + }; +} + static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, unsigned int num_irqs, void *data) { @@ -2039,46 +2063,15 @@ static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, err = irq_domain_set_hwirq_and_chip(domain, virq, event->id, - &pmc->irq, pmc); - - /* - * GPIOs don't have an equivalent interrupt in the - * parent controller (GIC). However some code, such - * as the one in irq_get_irqchip_state(), require a - * valid IRQ chip to be set. Make sure that's the - * case by passing NULL here, which will install a - * dummy IRQ chip for the interrupt in the parent - * domain. - */ - if (domain->parent) - irq_domain_set_hwirq_and_chip(domain->parent, - virq, 0, NULL, - NULL); - + &pmc_irqchip, pmc); + if (!err) + trim_hierarchy(virq, domain->parent); break; } } - /* - * For interrupts that don't have associated wake events, assign a - * dummy hardware IRQ number. This is used in the ->irq_set_type() - * and ->irq_set_wake() callbacks to return early for these IRQs. - */ - if (i == soc->num_wake_events) { - err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX, - &pmc_irqchip, pmc); - - /* - * Interrupts without a wake event don't have a corresponding - * interrupt in the parent controller (GIC). Pass NULL for the - * chip here, which causes a dummy IRQ chip to be installed - * for the interrupt in the parent domain, to make this - * explicit. - */ - if (domain->parent) - irq_domain_set_hwirq_and_chip(domain->parent, virq, 0, - NULL, NULL); - } + if (i == soc->num_wake_events) + trim_hierarchy(virq, domain); return err; } @@ -2094,9 +2087,6 @@ static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) unsigned int offset, bit; u32 value; - if (data->hwirq == ULONG_MAX) - return 0; - offset = data->hwirq / 32; bit = data->hwirq % 32; @@ -2131,9 +2121,6 @@ static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) unsigned int offset, bit; u32 value; - if (data->hwirq == ULONG_MAX) - return 0; - offset = data->hwirq / 32; bit = data->hwirq % 32; @@ -2174,10 +2161,6 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) unsigned int offset, bit; u32 value; - /* nothing to do if there's no associated wake event */ - if (WARN_ON(data->hwirq == ULONG_MAX)) - return 0; - offset = data->hwirq / 32; bit = data->hwirq % 32; @@ -2205,10 +2188,6 @@ static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); u32 value; - /* nothing to do if there's no associated wake event */ - if (data->hwirq == ULONG_MAX) - return 0; - value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); switch (type) { -- 2.28.0