Received: by 2002:a05:6a10:6744:0:0:0:0 with SMTP id w4csp342976pxu; Wed, 7 Oct 2020 04:47:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7hcMCCfSRi4w7Y/AyYboOdr2XOYlKLwGx4DOUpsGp+Vhyq3uwjnFQmABjtHDPGvj5faad X-Received: by 2002:a17:906:eb01:: with SMTP id mb1mr2871484ejb.124.1602071258980; Wed, 07 Oct 2020 04:47:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602071258; cv=none; d=google.com; s=arc-20160816; b=SZ+vmYwJPybhHoDA9Feo5qQzI4TwIaQmv4pgcl64gFEQP3yJul5eKar0iPBSGJnfdR 72L14aLNRo/A06Dxz2evL08ff+rqhhH9lCrZaMf5gK4NuFdna8RpQOyENT62NX6CmDpg F1inOXFpyWKGfheIfc79TxuxABz8ydakRe5nHyK7zG9GY7aCh+R8a3KHPUUAiLM+476d v6l9wqdZma+0oCbaTn7E10J2VJ90Ibyk/aL/9Wz1vo0rbN/d5dNizJ0yXEx8Zsa4LoW9 r3yE/zlxSi+Vbmfxgvw87FGMq8ZScSP8Fgy88+r5khni8mv0BKBLZKP2dQtxEpVE06um eMQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=C0b8qOYsqDKS/518qMzUtz1z+8KWY2Z217g5ToafA0s=; b=yhG213ItAlerAHopRCzmzE/qqzxyPvAazfZK5w+zNIHHAebhSjOKBpyDogDEUvDcon 86EIxUBQ2LS6TH2/7Ro2Kf0wGGwBUfLUrf60MyczwI9CaDVo4/MoKWl+d4nxoPI9dj2r 1bSW/Dpv0VoyH6mdYZd3P4TtWN8kJTq3uzecprRKgghAs7uqVUnigH4QEHQu4vU9Z1zY DdjRTYghBC6qUJZvCeiXgcdQLETGvf0reFBRllPUVf8mXjxM9kPvcXo9evkB+xfmAvrs psJYOmNLZfci9/qSrCh9JgLdYcpQGumPbUbBqhbM1Li4YvQ9H8ygW3Rgie2k7isubLMV Q12Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bj4si786290ejb.474.2020.10.07.04.47.14; Wed, 07 Oct 2020 04:47:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727994AbgJGLnk (ORCPT + 99 others); Wed, 7 Oct 2020 07:43:40 -0400 Received: from foss.arm.com ([217.140.110.172]:42440 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726096AbgJGLnk (ORCPT ); Wed, 7 Oct 2020 07:43:40 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 996B831B; Wed, 7 Oct 2020 04:43:39 -0700 (PDT) Received: from bogus (unknown [10.57.54.133]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8315C3F71F; Wed, 7 Oct 2020 04:43:37 -0700 (PDT) Date: Wed, 7 Oct 2020 12:43:35 +0100 From: Sudeep Holla To: Viresh Kumar Cc: Jassi Brar , Jassi Brar , ALKML , DTML , LKML , Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: Re: [PATCH 4/4] mailbox: arm_mhu: Add ARM MHU doorbell driver Message-ID: <20201007114335.5j7cq4cv4iwbam3g@bogus> References: <20200928114445.19689-1-sudeep.holla@arm.com> <20200928114445.19689-5-sudeep.holla@arm.com> <20201007060525.ya6limypf6ggmtae@vireshk-i7> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201007060525.ya6limypf6ggmtae@vireshk-i7> User-Agent: NeoMutt/20171215 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 07, 2020 at 11:35:25AM +0530, Viresh Kumar wrote: > On 28-09-20, 12:44, Sudeep Holla wrote: > > The MHU drives the signal using a 32-bit register, with all 32 bits > > logically ORed together. The MHU provides a set of registers to enable > > software to set, clear, and check the status of each of the bits of this > > register independently. The use of 32 bits for each interrupt line > > enables software to provide more information about the source of the > > interrupt. For example, each bit of the register can be associated with > > a type of event that can contribute to raising the interrupt. > > > > This patch adds a separate the MHU controller driver for doorbel mode > > of operation using the extended DT binding to add support the same. > > > > Signed-off-by: Sudeep Holla > > --- > > drivers/mailbox/Makefile | 2 +- > > drivers/mailbox/arm_mhu_db.c | 359 +++++++++++++++++++++++++++++++++++ > > Please put an entry in MAINTAINERS as well for this. Sure. -- Regards, Sudeep