Received: by 2002:a05:6a10:6744:0:0:0:0 with SMTP id w4csp828102pxu; Wed, 7 Oct 2020 17:49:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx76l0w5Oeo066CblCdUobt/wOFhDOsmOUH513ApO+ZsJSMPH2OMPtd/dHrtM8+eNoyhB4Q X-Received: by 2002:a17:906:489b:: with SMTP id v27mr6322640ejq.315.1602118175385; Wed, 07 Oct 2020 17:49:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602118175; cv=none; d=google.com; s=arc-20160816; b=JJacccQ+DSw20P6A3dFuYY5NJmE9qo7Wz4PnF/c/NYrF3aattpycMGN7nBlm2YZjOV GUn0Qi9qHa7MLtieeAT/3GEwUiL4oR7SAowKIjNWQSuiOWbCBURUMygVFzbAkrXiXh3P NbO/I5JkmoB9C85vmE3gvku3W59a1/Ai5JIwku4EC8zd9WptXcMuQW3MYfnfeb7popTo 5aaekrhpOoc/hdUBnmj9x+yPYQUGkyMAhuXT/u3cuaNHSnoPC9YWRN+Nz4i1EJG2JYN2 hr2yrEbYxTRjEwvMaHhL86X71XDM2h52oIxtDcnaAS9fRSoX+l1GMCAKq2yxhHe7pSi6 70EQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=8TofdA+s9lTNYe6tSWMHvc1acqj6O7nZ+7UG+dfmbww=; b=jG6T0KI03a+e9fddQgZVS4kizr8AWkBuzlDFQ94fd6ZiWjGJE7/epgDKdb0D464/Pq mcPOid312eLSuhlyErN7FUc9+9u2Dq7tqKQnbq0kNy9Z4sc+Qt/Hq74bO0uI+5Y85we5 Em3uQ5Tr9zpiSrxwD6ghqU1bZfOB3aswPqibQX7Do2BaQvP2wz2hXQ9LAqfpkk1BStwe 3/TY9KLhSORUcshDDKAT5qmVk4rMu6iaitsTVksNStFEoJk2n6xK+jEvCmYU5r/VK4QU 6oTPKVtaA7i9Ec40C8nIs8B0Xk2AAziRPyiNyMxXDPbfR+oO4jo3hle22Rf0zQH2stov DO5Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d21si2502948eje.284.2020.10.07.17.49.12; Wed, 07 Oct 2020 17:49:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727080AbgJHA00 (ORCPT + 99 others); Wed, 7 Oct 2020 20:26:26 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:48936 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726129AbgJHA0Z (ORCPT ); Wed, 7 Oct 2020 20:26:25 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kQJlF-000cLX-2X; Thu, 08 Oct 2020 02:26:21 +0200 Date: Thu, 8 Oct 2020 02:26:21 +0200 From: Andrew Lunn To: Vivek Unune Cc: devicetree@vger.kernel.org, Hauke Mehrtens , =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= , linux-kernel@vger.kernel.org, Rob Herring , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl Message-ID: <20201008002621.GF112961@lunn.ch> References: <6687de05226dd055ee362933d4841a12b038792d.1601655904.git.npcomplete13@gmail.com> <20201007210134.GD112961@lunn.ch> <20201007214633.GA1972@ubuntu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201007214633.GA1972@ubuntu> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 07, 2020 at 05:46:33PM -0400, Vivek Unune wrote: > On Wed, Oct 07, 2020 at 11:01:34PM +0200, Andrew Lunn wrote: > > On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote: > > > Forgo the use of mmioreg mdio mux infavor of the pinctrl > > > > Hi Vivek > > > > Could you add some more details please. I don't know this > > hardware. I'm assuming there are two MDIO busses, external as talked > > about in the comments, and an internal one? And for this hardware you > > only need one of them? But i don't see what pinmux has to do with > > this? > Hi Andrew, > > There are indeed two mdio busses. To access the external bus, 9th bit > of the mdio register has to be set. And to enable mii function, > one has to set the registers 6 & 7 which is part of the pin controller. > Earlier the pin controller was not defined and I resorted to use a > combination of memory mapped io mux to change desired bits. > > Now that we have a pin controller - which is resposnsible for other > functionality such as pwm, i2c, uart2, it makes sense to have a consistent > device tree What makes it confusing is that you make multiple changes at once. It would be easier to follow if you added the pinmux and removed the mmioreg mux, and move the switch into the mdio-bus-mux node. Then in a second patch rearrange the mdio-bus-mux. Small simple steps, with good commit messages are much easier to follow and say, Yes, this is correct. Andrew