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From:   "Ardelean, Alexandru" <alexandru.Ardelean@analog.com>
To:     Rob Herring <robh@kernel.org>
CC:     "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Hennerich, Michael" <Michael.Hennerich@analog.com>,
        "lars@metafoo.de" <lars@metafoo.de>,
        "sboyd@kernel.org" <sboyd@kernel.org>,
        "mturquette@baylibre.com" <mturquette@baylibre.com>,
        "mdf@kernel.org" <mdf@kernel.org>,
        "ardeleanalex@gmail.com" <ardeleanalex@gmail.com>
Subject: RE: [PATCH] dt-bindings: clock: adi,axi-clkgen: convert old binding
 to yaml format
Thread-Topic: [PATCH] dt-bindings: clock: adi,axi-clkgen: convert old binding
 to yaml format
Thread-Index: AQHWl89UuvXdY5bmPEyPgI4kiypprqmLDduAgAJro8A=
Date:   Thu, 8 Oct 2020 09:28:03 +0000
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References: <20201001085035.82938-1-alexandru.ardelean@analog.com>
 <20201006202449.GA2769322@bogus>
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> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Tuesday, October 6, 2020 11:25 PM
> To: Ardelean, Alexandru <alexandru.Ardelean@analog.com>
> Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Hennerich, Michael
> <Michael.Hennerich@analog.com>; lars@metafoo.de; sboyd@kernel.org;
> mturquette@baylibre.com; mdf@kernel.org
> Subject: Re: [PATCH] dt-bindings: clock: adi,axi-clkgen: convert old bind=
ing to
> yaml format
>=20
> On Thu, Oct 01, 2020 at 11:50:35AM +0300, Alexandru Ardelean wrote:
> > This change converts the old binding for the AXI clkgen driver to a
> > yaml format.
> >
> > As maintainers, added:
> >  - Lars-Peter Clausen <lars@metafoo.de> - as original author of driver =
&
> >    binding
>=20
> Do you have permission for relicensing? The default was GPL-2.0.

I talked to Michael Hennerich [he's cc-ed], and we have permission from his=
 side.
I think Lars would need to provide permission as well, as the author.
If we won't have a reply from him [after by some time-frame] I'll leave it =
as GPL-2.0.
I'm a bit clumsy about licensing in general; and I don't care about it all =
that much.

>=20
> >  - Michael Hennerich <michael.hennerich@analog.com> - as supporter of
> >    Analog Devices drivers
> >
> > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> > ---
> >  .../bindings/clock/adi,axi-clkgen.yaml        | 52 +++++++++++++++++++
> >  .../devicetree/bindings/clock/axi-clkgen.txt  | 25 ---------
> >  2 files changed, 52 insertions(+), 25 deletions(-)  create mode
> > 100644 Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
> >  delete mode 100644
> > Documentation/devicetree/bindings/clock/axi-clkgen.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
> > b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
> > new file mode 100644
> > index 000000000000..45497f370cb3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
> > @@ -0,0 +1,52 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://urldefense.com/v3/__http://devicetree.org/schemas/clock/adi,a
> > +xi-
> clkgen.yaml*__;Iw!!A3Ni8CS0y2Y!s_aQs5F13Tud7X5wmDjgyOhkPGGpnQgdtN7
> > +apmY8mrX_fgQOlQvZTtRGBSIpmJtDghVa8A$
> > +$schema:
> > +https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.y
> >
> +aml*__;Iw!!A3Ni8CS0y2Y!s_aQs5F13Tud7X5wmDjgyOhkPGGpnQgdtN7apmY8
> mrX_fg
> > +QOlQvZTtRGBSIpmJuCLAwQnQ$
> > +
> > +title: Binding for Analog Devices AXI clkgen pcore clock generator
> > +
> > +maintainers:
> > +  - Lars-Peter Clausen <lars@metafoo.de>
> > +  - Michael Hennerich <michael.hennerich@analog.com>
> > +
> > +description: |
> > +  The axi_clkgen IP core is a software programmable clock generator,
> > +  that can be synthesized on various FPGA platforms.
> > +
> > +  Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - adi,axi-clkgen-2.00.a
> > +
> > +  clocks:
> > +    description:
> > +      Phandle and clock specifier for the parent clock(s).
>=20
> Drop, that's every 'clocks'.
>=20
> > This must either
> > +      reference one clock if only the first clock input is connected o=
r two
> > +      if both clock inputs are connected. For the later case the clock
> > +      connected to the first input must be specified first.
>=20
> That doesn't really say what the 2 clocks are.
>=20
> > +    minItems: 1
> > +    maxItems: 2
> > +
> > +  '#clock-cells':
> > +    const: 0
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - '#clock-cells'
>=20
> additionalProperties: false
>=20
> > +
> > +examples:
> > +  - |
> > +    clock@ff000000 {
>=20
> clock-controller@...
>=20
> > +      compatible =3D "adi,axi-clkgen-2.00.a";
> > +      #clock-cells =3D <0>;
> > +      reg =3D <0xff000000 0x1000>;
> > +      clocks =3D <&osc 1>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt
> > b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
> > deleted file mode 100644
> > index aca94fe9416f..000000000000
> > --- a/Documentation/devicetree/bindings/clock/axi-clkgen.txt
> > +++ /dev/null
> > @@ -1,25 +0,0 @@
> > -Binding for the axi-clkgen clock generator
> > -
> > -This binding uses the common clock binding[1].
> > -
> > -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> > -
> > -Required properties:
> > -- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.0=
0.a".
> > -- #clock-cells : from common clock binding; Should always be set to 0.
> > -- reg : Address and length of the axi-clkgen register set.
> > -- clocks : Phandle and clock specifier for the parent clock(s). This m=
ust
> > -	either reference one clock if only the first clock input is connected=
 or
> two
> > -	if both clock inputs are connected. For the later case the clock
> connected
> > -	to the first input must be specified first.
> > -
> > -Optional properties:
> > -- clock-output-names : From common clock binding.
> > -
> > -Example:
> > -	clock@ff000000 {
> > -		compatible =3D "adi,axi-clkgen";
> > -		#clock-cells =3D <0>;
> > -		reg =3D <0xff000000 0x1000>;
> > -		clocks =3D <&osc 1>;
> > -	};
> > --
> > 2.17.1
> >