Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
IronPort-SDR: 0Z9uZnzg3TOLv8yuUtQ33msyBJBj/9R28t1lHSilAqBe6Td4mWniU5ClWLVr4E08uzhRULTdyU
 iEePbQ37LnwcBhBy7jTubiBJ2XV6DGIGbmXFMSeuSENAAmnEIBbUpkihBQ1m+FTp1UYFsdtkIl
 y0hn6TNRK2+sXxxn5rxkw/aNNCaplpn6iztY4MC/Xwr+jqTr5SIVUSr4hmkh2N1Mf++Zd6KRmh
 KQY2Et0rRZBYpJGsCctDyO8TtN4C+JayEirTba/TnHH+zab8MfCeuFjF+YctW1OpyaGzwzSFmD
 oLw=
References: <20201007111145.2306213-1-lars.povlsen@microchip.com> <20201007111145.2306213-2-lars.povlsen@microchip.com> <CACRpkda0RAK2gp-ZB6LDxAnQP3=VGrsfqkfV0=3FiSFfNhOmjA@mail.gmail.com>
From:   Lars Povlsen <lars.povlsen@microchip.com>
To:     Linus Walleij <linus.walleij@linaro.org>
CC:     Lars Povlsen <lars.povlsen@microchip.com>,
        Rob Herring <robh+dt@kernel.org>,
        Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Alexandre Belloni <alexandre.belloni@bootlin.com>
Subject: Re: [PATCH v4 1/3] dt-bindings: pinctrl: Add bindings for pinctrl-mchp-sgpio driver
In-Reply-To: <CACRpkda0RAK2gp-ZB6LDxAnQP3=VGrsfqkfV0=3FiSFfNhOmjA@mail.gmail.com>
Date:   Thu, 8 Oct 2020 13:43:48 +0200
Message-ID: <87eem9x7rf.fsf@soft-dev15.microsemi.net>
MIME-Version: 1.0
Content-Type: text/plain
Precedence: bulk


Linus Walleij writes:

> Hi Lars,
>
> a new version of the patch set arrives while I'm reviewing, haha :D

Well, luckily not too much changed per Rob's input.

>
> On Wed, Oct 7, 2020 at 1:12 PM Lars Povlsen <lars.povlsen@microchip.com> wrote:
>
>> This adds DT bindings for the Microsemi/Microchip SGPIO controller,
>> bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and
>> mscc,luton-sgpio.
>>
>> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
>
> (...)
>> +      reg:
>> +        description: |
>> +          The GPIO bank number. "0" is designates the input pin bank,
>> +          "1" the output bank.
>> +        maxItems: 1
>
> Excellent.
>
>> +      '#gpio-cells':
>> +        const: 3
>
> So I thought you needed three cells exactly because the
> middle cell would get you the bank. That you now have in
> reg. So what about using the standard twocell?

I think I answered that in the 'v3 2/3' reply.

Basically the pins are addressed with two indices, and there are good
reasons to expose these to the GPIO cells, f.ex. hardware documentation
cross reference.

---Lars

>
> Yours,
> Linus Walleij

-- 
Lars Povlsen,
Microchip