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From:   Linus Walleij <linus.walleij@linaro.org>
Date:   Thu, 8 Oct 2020 22:54:12 +0200
Message-ID: <CACRpkdb2AamnF9h_FfFDhTBMz7W-gob98OOzrHOiovyoiBPWRw@mail.gmail.com>
Subject: Re: [PATCH v18 4/5] dt-bindings: remoteproc: Add documentation for
 ZynqMP R5 rproc bindings
To:     Ben Levinsky <BLEVINSK@xilinx.com>
Cc:     Catalin Marinas <catalin.marinas@arm.com>,
        Stefano Stabellini <stefanos@xilinx.com>,
        "Ed T. Mooring" <emooring@xilinx.com>,
        "sunnyliangjy@gmail.com" <sunnyliangjy@gmail.com>,
        Punit Agrawal <punit1.agrawal@toshiba.co.jp>,
        Michal Simek <michals@xilinx.com>,
        "michael.auchter@ni.com" <michael.auchter@ni.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        Mathieu Poirier <mathieu.poirier@linaro.org>,
        "linux-remoteproc@vger.kernel.org" <linux-remoteproc@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>
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On Thu, Oct 8, 2020 at 4:21 PM Ben Levinsky <BLEVINSK@xilinx.com> wrote:

> As you said, this is  just regular ARM TCM memory (as seen by the main AR=
M64 cluster).
> Yes I can add back the compatible string, though maybe just "tcm" or "xln=
x,tcm"

I mean that if it is an ARM standard feature it should be prefixed "arm,"

> That being said, we can change this around to couple the TCM bank nodes i=
nto the R5 as we have In our present, internal implementation at
> - https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetr=
ee/bindings/remoteproc/xilinx%2Czynqmp-r5-remoteproc.txt
> - https://github.com/Xilinx/linux-xlnx/blob/master/drivers/remoteproc/zyn=
qmp_r5_remoteproc.c
> the TCM nodes are coupled in the R5 but after some previous review on thi=
s list, it was moved to have the TCM nodes decoupled from the R5 node
>
> I am not sure what you mean on the Arm64 handling of TCM memory. Via the =
architecture of the SoC https://www.xilinx.com/support/documentation/user_g=
uides/ug1085-zynq-ultrascale-trm.pdf I know that the A53 cluster can see th=
e absolute addresses of the R5 cluster so the translation is *I think* done=
 as you describe with the CP15 instructions you listed.

It seems like the TCM memories are von Neumann type (either can
contain both code and
data) which removes one of my worries. According to this data sheet
they are also nothing
ARM-provided but a Xilinx invention, and just happen to be hardcoded
at the same address
as TCM memories in ARM32, what a coincidence.

So I take it this is the correct view and you can proceed like this,
sorry for the fuzz.

Yours,
Linus Walleij